Commit eea087b8 authored by Iulian Gheorghiu's avatar Iulian Gheorghiu

Update project to the latest changes.

parent f9ec7aca
This diff is collapsed.
[General]
showNCD=true
showPgroups=true
showCongestion=false
showConnsSelect=false
showConnsBetween=true
showConnsOutside=true
showLPF=true
showREGIONs=true
showUGROUPs=true
showPARITIONs=true
showLogicalConnections=false
dontShowBBoxOverlapWarning=false
sceneInViewRect=@Variant(\0\0\0\x14\xc0\xa7\x94\xe2\xca\xbc\xfeI\xc0\x88/\xad\x87\xbb\x46rA\x5h\x9a\x33\x8b*\xf4@\xf9\xc6\x1\xb7\xd6\xc3\xde)
[SysIOView]
Type=100
Name=100
Pin=100
Bank=100
IO_TYPE=100
PULLMODE=100
DRIVE=100
SLEWRATE=100
CLAMP=100
OPENDRAIN=100
DIFFRESISTOR=100
DIFFDRIVE=100
BANK_VCCIO=100
HYSTERESIS=100
SortColumns="1,"
[PLLView]
Type=100
Name=100
SortColumns="2,"
[MemoryTreeView]
EBR%20Configuration=1022
Setting=1027
<?xml version="1.0" encoding="UTF-8"?>
<BaliProject version="3.2" title="XmegaCoreIpTstLattice" device="LCMXO3LF-6900C-5BG256C" default_implementation="impl1">
<Options/>
<Implementation title="impl1" dir="impl1" description="impl1" synthesis="lse" default_strategy="Strategy1">
<Options def_top="sim_uc" top="top_uc"/>
<Source name="top_uc.v" type="Verilog" type_short="Verilog">
<Options top_module="top_uc"/>
</Source>
<Source name="../VERILOG-UTIL-IP/xmega_core/mega_core_opt.v" type="Verilog" type_short="Verilog">
<Options/>
</Source>
<Source name="../VERILOG-UTIL-IP/xmega_core/sim_uc.v" type="Verilog" type_short="Verilog">
<Options/>
</Source>
<Source name="../VERILOG-UTIL-IP/xmega_core/io/rtc_s.v" type="Verilog" type_short="Verilog">
<Options/>
</Source>
<Source name="../VERILOG-UTIL-IP/xmega_core/io/pio_s.v" type="Verilog" type_short="Verilog">
<Options/>
</Source>
<Source name="../VERILOG-UTIL-IP/xmega_core/io/io_s_h.v" type="Verilog" type_short="Verilog">
<Options/>
</Source>
<Source name="../VERILOG-UTIL-IP/helpers/memory.v" type="Verilog" type_short="Verilog">
<Options/>
</Source>
<Source name="core1ROM.mem" type="Unknown Type" type_short="Unknown">
<Options/>
</Source>
<Source name="impl1/impl1.xcf" type="Programming Project File" type_short="Programming">
<Options/>
</Source>
<Source name="sim/sim.spf" type="Simulation Project File" type_short="SPF">
<Options/>
</Source>
<Source name="untitled.rva" type="Reveal Analyzer Project File" type_short="RVA" excluded="TRUE">
<Options/>
</Source>
<Source name="xmega.rvl" type="Reveal" type_short="Reveal" excluded="TRUE">
<Options/>
</Source>
<Source name="XmegaCoreIpTstLattice.lpf" type="Logic Preference" type_short="LPF">
<Options/>
</Source>
</Implementation>
<Strategy name="Strategy1" file="XmegaCoreIpTstLattice1.sty"/>
</BaliProject>
[Runmanager]
Geometry=@ByteArray(\x1\xd9\xd0\xcb\0\x1\0\0\0\0\0\0\0\0\0\0\0\0\x1\x1c\0\0\0\xd8\0\0\0\0\0\0\0\0\xff\xff\xff\xff\xff\xff\xff\xff\0\0\0\0\0\0)
windowState=@ByteArray(\0\0\0\xff\0\0\0\0\xfd\0\0\0\0\0\0\x5\xdd\0\0\x2\x98\0\0\0\x4\0\0\0\x4\0\0\0\b\0\0\0\b\xfc\0\0\0\x1\0\0\0\0\0\0\0\x1\xff\xff\xff\xff\x3\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0)
headerState=@ByteArray(\0\0\0\xff\0\0\0\0\0\0\0\x1\0\0\0\x1\0\0\0\0\x1\0\0\0\0\0\0\0\0\0\0\0\x16\0\xe0?\0\0\0\t\0\0\0\x10\0\0\0\x64\0\0\0\xf\0\0\0\x64\0\0\0\xe\0\0\0\x64\0\0\0\r\0\0\0\x64\0\0\0\x15\0\0\0\x64\0\0\0\x14\0\0\0\x64\0\0\0\x13\0\0\0\x64\0\0\0\x12\0\0\0\x64\0\0\0\x11\0\0\0\x64\0\0\x5\xd9\0\0\0\x16\x1\x1\0\x1\0\0\0\0\0\0\0\0\0\0\0\0\x64\xff\xff\xff\xff\0\0\0\x81\0\0\0\0\0\0\0\x4\0\0\0#\0\0\0\x1\0\0\0\x2\0\0\x4L\0\0\0\v\0\0\0\0\0\0\x1j\0\0\0\x1\0\0\0\0\0\0\0\0\0\0\0\t\0\0\0\0)
windowState=@ByteArray(\0\0\0\xff\0\0\0\0\xfd\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\x4\0\0\0\x4\0\0\0\b\0\0\0\b\xfc\0\0\0\x1\0\0\0\0\0\0\0\x1\xff\xff\xff\xff\x3\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0)
headerState=@ByteArray(\0\0\0\xff\0\0\0\0\0\0\0\x1\0\0\0\x1\0\0\0\0\x1\0\0\0\0\0\0\0\0\0\0\0\x16\0\xe0?\0\0\0\t\0\0\0\x10\0\0\0\x64\0\0\0\xf\0\0\0\x64\0\0\0\xe\0\0\0\x64\0\0\0\r\0\0\0\x64\0\0\0\x15\0\0\0\x64\0\0\0\x14\0\0\0\x64\0\0\0\x13\0\0\0\x64\0\0\0\x12\0\0\0\x64\0\0\0\x11\0\0\0\x64\0\0\x4\xd3\0\0\0\x16\x1\x1\0\x1\0\0\0\0\0\0\0\0\0\0\0\0\x64\xff\xff\xff\xff\0\0\0\x81\0\0\0\0\0\0\0\x3\0\0\0#\0\0\0\x1\0\0\0\x2\0\0\x4\xb0\0\0\0\f\0\0\0\0\0\0\0\0\0\0\0\t\0\0\0\0)
[impl1%3CStrategy1%3E]
isChecked=true
isChecked=false
isHidden=false
isExpanded=false
[General]
Map.auto_tasks=MapTrace, MapVerilogSimFile
PAR.auto_tasks=PARTrace, IOTiming
Export.auto_tasks=TimingSimFileVlg, Bitgen, Jedecgen
EnableRealTimePIODRCOnSSV=true
AutoAssign=false
Map.auto_tasks=MapVerilogSimFile
Export.auto_tasks=Bitgen, Jedecgen
[General]
COLUMN_POS_INFO_NAME_-1_0=Prioritize
COLUMN_POS_INFO_NAME_-1_1=PIO Register
[General]
pin_sort_type=0
pin_sort_ascending=true
sig_sort_type=0
sig_sort_ascending=true
active_Sheet=Port Assignments
[Port%20Assignments]
Name="140,0"
Group%20By="84,1"
Pin="67,2"
BANK="62,3"
BANK_VCC="90,4"
VREF="60,5"
IO_TYPE="147,6"
PULLMODE="97,7"
DRIVE="67,8"
SLEWRATE="92,9"
CLAMP="71,10"
OPENDRAIN="97,11"
DIFFRESISTOR="114,12"
DIFFDRIVE="92,13"
HYSTERESIS="101,14"
Outload%20%28pF%29="103,15"
MaxSkew="87,16"
Clock%20Load%20Only="121,17"
SwitchingID="100,18"
Ground%20plane%20PCB%20noise%20%28mV%29="196,19"
Power%20plane%20PCB%20noise%20%28mV%29="190,20"
SSO%20Allowance%28%25%29="138,21"
sort_columns="DRIVE,Ascending"
[Pin%20Assignments]
Pin="90,0"
Pad%20Name="89,1"
Dual%20Function="261,2"
Polarity="77,3"
BANK="0,4"
BANK_VCC="90,5"
IO_TYPE="147,6"
Signal%20Name="102,7"
Signal%20Type="98,8"
sort_columns="Pin,Ascending"
[Clock%20Resource]
Clock%20Type="100,ELLIPSIS"
Clock%20Name="201,ELLIPSIS"
Selection="100,ELLIPSIS"
[Global%20Preferences]
Preference%20Name="231,ELLIPSIS"
Preference%20Value="236,ELLIPSIS"
[Cell%20Mapping]
Type="100,ELLIPSIS"
Name="100,ELLIPSIS"
Din\Dout="100,ELLIPSIS"
PIO%20Register="100,ELLIPSIS"
[Route%20Priority]
Type="100,ELLIPSIS"
Name="100,ELLIPSIS"
Prioritize="100,ELLIPSIS"
[Timing%20Preferences]
Preference%20Name="138,ELLIPSIS"
Preference%20Value="105,ELLIPSIS"
Preference%20Unit="1250,ELLIPSIS"
[Group]
Group%20Type\Name="134,ELLIPSIS"
Value="1359,ELLIPSIS"
[Misc%20Preferences]
Preference%20Name="117,ELLIPSIS"
Preference%20Value="1376,ELLIPSIS"
/*
* CTest.c
*
* Created: 3/13/2018 10:14:25 PM
* Author: Iulian Gheorghiu
*/
#include <avr/io.h>
#include <avr/interrupt.h>
#include "io_defs.h"
//#define delay_cycles 2
#define delay_cycles 250//0x00040000
#define RTC_PERIOD (CPU_FREQ / 1000)
volatile unsigned long long rtc_cnt = 0;
void delay(unsigned long time)
{
unsigned long long time_to_tick = rtc_cnt + time;
while(time_to_tick > rtc_cnt)
{
asm("wdr");
}
}
#define SET OUTCLR
#define CLEAR OUTSET
void left_to_right(unsigned long times)
{
FPGA_PORTB.CLEAR = 0xFF;
delay(times);
FPGA_PORTB.SET = 0b00000001;
delay(times);
FPGA_PORTB.CLEAR = 0b00000001;
FPGA_PORTB.SET = 0b00000010;
delay(times);
FPGA_PORTB.CLEAR = 0b00000010;
FPGA_PORTB.SET = 0b00000100;
delay(times);
FPGA_PORTB.CLEAR = 0b00000100;
FPGA_PORTB.SET = 0b00001000;
delay(times);
FPGA_PORTB.CLEAR = 0b00001000;
FPGA_PORTB.SET = 0b00010000;
delay(times);
FPGA_PORTB.CLEAR = 0b00010000;
FPGA_PORTB.SET = 0b00100000;
delay(times);
FPGA_PORTB.CLEAR = 0b00100000;
FPGA_PORTB.SET = 0b01000000;
delay(times);
FPGA_PORTB.CLEAR = 0b01000000;
FPGA_PORTB.SET = 0b10000000;
delay(times);
FPGA_PORTB.CLEAR = 0xFF;
delay(times);
}
void right_to_left(unsigned long times)
{
FPGA_PORTB.CLEAR = 0xFF;
delay(times);
FPGA_PORTB.SET = 0b10000000;
delay(times);
FPGA_PORTB.CLEAR = 0b10000000;
FPGA_PORTB.SET = 0b01000000;
delay(times);
FPGA_PORTB.CLEAR = 0b01000000;
FPGA_PORTB.SET = 0b00100000;
delay(times);
FPGA_PORTB.CLEAR = 0b00100000;
FPGA_PORTB.SET = 0b00010000;
delay(times);
FPGA_PORTB.CLEAR = 0b00010000;
FPGA_PORTB.SET = 0b00001000;
delay(times);
FPGA_PORTB.CLEAR = 0b00001000;
FPGA_PORTB.SET = 0b00000100;
delay(times);
FPGA_PORTB.CLEAR = 0b00000100;
FPGA_PORTB.SET = 0b00000010;
delay(times);
FPGA_PORTB.CLEAR = 0b00000010;
FPGA_PORTB.SET = 0b00000001;
delay(times);
FPGA_PORTB.CLEAR = 0xFF;
delay(times);
}
void center_to_center(unsigned long times)
{
FPGA_PORTB.CLEAR = 0xFF;
delay(times);
FPGA_PORTB.SET = 0b10000001;
delay(times);
FPGA_PORTB.CLEAR = 0b10000001;
FPGA_PORTB.SET = 0b01000010;
delay(times);
FPGA_PORTB.CLEAR = 0b01000010;
FPGA_PORTB.SET = 0b00100100;
delay(times);
FPGA_PORTB.CLEAR = 0b00100100;
FPGA_PORTB.SET = 0b00011000;
delay(times);
FPGA_PORTB.CLEAR = 0b00011000;
FPGA_PORTB.SET = 0b00100100;
delay(times);
FPGA_PORTB.CLEAR = 0b00100100;
FPGA_PORTB.SET = 0b01000010;
delay(times);
FPGA_PORTB.CLEAR = 0b01000010;
FPGA_PORTB.SET = 0b10000001;
delay(times);
FPGA_PORTB.CLEAR = 0xFF;
delay(times);
}
int main(void)
{
asm("sei");
//FPGA_PORTA.DIR = 0;
//FPGA_PORTA.PIN0CTRL = FPGA_PORT_ISC_RISING_gc;
//FPGA_PORTA.PIN1CTRL = FPGA_PORT_ISC_RISING_gc;
//FPGA_PORTA.PIN2CTRL = FPGA_PORT_ISC_RISING_gc;
//FPGA_PORTA.INTMASK = 0x07;
FPGA_PORTA.DIR = 0;
FPGA_PORTB.DIR = 0xFF;
FPGA_PORTB.OUT = 0xAA;
FPGA_RTC.RTC_PERIOD_BYTE3 = (unsigned char)(RTC_PERIOD >> 24);
FPGA_RTC.RTC_PERIOD_BYTE2 = (unsigned char)(RTC_PERIOD >> 16);
FPGA_RTC.RTC_PERIOD_BYTE1 = (unsigned char)(RTC_PERIOD >> 8);
FPGA_RTC.RTC_PERIOD_BYTE0 = (unsigned char)RTC_PERIOD;
//FPGA_UARTA.BAUDCTRLB = ((CPU_FREQ / 16 / 1000000) - 1) >> 8;
//FPGA_UARTA.BAUDCTRLA = ((CPU_FREQ / 16 / 1000000)-1);
//FPGA_UARTA.CTRLA = FPGA_USART_RXCINTLVL_HI_gc;
//FPGA_UARTA.CTRLB = FPGA_USART_RXEN_bm | FPGA_USART_TXEN_bm;
//FPGA_UARTA.DATA = 0xAA;
while(1)
{
left_to_right(delay_cycles);
right_to_left(delay_cycles);
center_to_center(delay_cycles);
}
}
ISR(RTC_vect)
{
rtc_cnt++;
}
/*ISR(PORTA_vect)
{
unsigned char tmp = FPGA_PORTB.OUT;
unsigned char tmp_flags = FPGA_PORTA.INTFLAGS;
if(tmp_flags & 0x01)
{
FPGA_PORTA.INTFLAGS = 0x01;
asm("sei");
center_to_center(delay_cycles);
}
if(tmp_flags & 0x02)
{
FPGA_PORTA.INTFLAGS = 0x02;
asm("sei");
left_to_right(delay_cycles);
}
if(tmp_flags & 0x04)
{
FPGA_PORTA.INTFLAGS = 0x04;
asm("sei");
right_to_left(delay_cycles);
}
FPGA_PORTB.OUT = tmp;
}*/
/*ISR(PORTB_vect)
{
}
ISR(PORTC_vect)
{
}*/
/*ISR(UART_A_RXC_vect)
{
FPGA_UARTA.DATA = FPGA_UARTA.DATA;
}*/
CTest.d CTest.o: .././CTest.c \
c:\program\ files\ (x86)\atmel\atmel\ toolchain\avr8\ gcc\native\3.4.1061\avr8-gnu-toolchain\avr\include\avr\io.h \
c:\program\ files\ (x86)\atmel\atmel\ toolchain\avr8\ gcc\native\3.4.1061\avr8-gnu-toolchain\avr\include\avr\sfr_defs.h \
c:\program\ files\ (x86)\atmel\atmel\ toolchain\avr8\ gcc\native\3.4.1061\avr8-gnu-toolchain\avr\include\inttypes.h \
c:\program\ files\ (x86)\atmel\atmel\ toolchain\avr8\ gcc\native\3.4.1061\avr8-gnu-toolchain\lib\gcc\avr\4.8.1\include\stdint.h \
c:\program\ files\ (x86)\atmel\atmel\ toolchain\avr8\ gcc\native\3.4.1061\avr8-gnu-toolchain\avr\include\stdint.h \
c:\program\ files\ (x86)\atmel\atmel\ toolchain\avr8\ gcc\native\3.4.1061\avr8-gnu-toolchain\avr\include\avr\iox8e5.h \
c:\program\ files\ (x86)\atmel\atmel\ toolchain\avr8\ gcc\native\3.4.1061\avr8-gnu-toolchain\avr\include\avr\portpins.h \
c:\program\ files\ (x86)\atmel\atmel\ toolchain\avr8\ gcc\native\3.4.1061\avr8-gnu-toolchain\avr\include\avr\common.h \
c:\program\ files\ (x86)\atmel\atmel\ toolchain\avr8\ gcc\native\3.4.1061\avr8-gnu-toolchain\avr\include\avr\version.h \
c:\program\ files\ (x86)\atmel\atmel\ toolchain\avr8\ gcc\native\3.4.1061\avr8-gnu-toolchain\avr\include\avr\xmega.h \
c:\program\ files\ (x86)\atmel\atmel\ toolchain\avr8\ gcc\native\3.4.1061\avr8-gnu-toolchain\avr\include\avr\fuse.h \
c:\program\ files\ (x86)\atmel\atmel\ toolchain\avr8\ gcc\native\3.4.1061\avr8-gnu-toolchain\avr\include\avr\lock.h \
c:\program\ files\ (x86)\atmel\atmel\ toolchain\avr8\ gcc\native\3.4.1061\avr8-gnu-toolchain\avr\include\avr\interrupt.h \
.././io_defs.h .././xio.h
c:\program\ files\ (x86)\atmel\atmel\ toolchain\avr8\ gcc\native\3.4.1061\avr8-gnu-toolchain\avr\include\avr\io.h:
c:\program\ files\ (x86)\atmel\atmel\ toolchain\avr8\ gcc\native\3.4.1061\avr8-gnu-toolchain\avr\include\avr\sfr_defs.h:
c:\program\ files\ (x86)\atmel\atmel\ toolchain\avr8\ gcc\native\3.4.1061\avr8-gnu-toolchain\avr\include\inttypes.h:
c:\program\ files\ (x86)\atmel\atmel\ toolchain\avr8\ gcc\native\3.4.1061\avr8-gnu-toolchain\lib\gcc\avr\4.8.1\include\stdint.h:
c:\program\ files\ (x86)\atmel\atmel\ toolchain\avr8\ gcc\native\3.4.1061\avr8-gnu-toolchain\avr\include\stdint.h:
c:\program\ files\ (x86)\atmel\atmel\ toolchain\avr8\ gcc\native\3.4.1061\avr8-gnu-toolchain\avr\include\avr\iox8e5.h:
c:\program\ files\ (x86)\atmel\atmel\ toolchain\avr8\ gcc\native\3.4.1061\avr8-gnu-toolchain\avr\include\avr\portpins.h:
c:\program\ files\ (x86)\atmel\atmel\ toolchain\avr8\ gcc\native\3.4.1061\avr8-gnu-toolchain\avr\include\avr\common.h:
c:\program\ files\ (x86)\atmel\atmel\ toolchain\avr8\ gcc\native\3.4.1061\avr8-gnu-toolchain\avr\include\avr\version.h:
c:\program\ files\ (x86)\atmel\atmel\ toolchain\avr8\ gcc\native\3.4.1061\avr8-gnu-toolchain\avr\include\avr\xmega.h:
c:\program\ files\ (x86)\atmel\atmel\ toolchain\avr8\ gcc\native\3.4.1061\avr8-gnu-toolchain\avr\include\avr\fuse.h:
c:\program\ files\ (x86)\atmel\atmel\ toolchain\avr8\ gcc\native\3.4.1061\avr8-gnu-toolchain\avr\include\avr\lock.h:
c:\program\ files\ (x86)\atmel\atmel\ toolchain\avr8\ gcc\native\3.4.1061\avr8-gnu-toolchain\avr\include\avr\interrupt.h:
.././io_defs.h:
.././xio.h:
:1000000055C00000BAC1000061C000005FC0000020
:100010005DC000005BC0000059C0000057C0000078
:1000200055C0000053C0000051C000004FC0000088
:100030004DC000004BC0000049C0000047C0000098
:1000400045C0000043C0000041C000003FC00000A8
:100050003DC000003BC0000039C0000037C00000B8
:1000600035C0000033C0000031C000002FC00000C8
:100070002DC000002BC0000029C0000027C00000D8
:1000800025C0000023C0000021C000001FC00000E8
:100090001DC000001BC0000019C0000017C00000F8
:1000A00015C0000013C0000011C0000011241FBEC5
:1000B000CFEFCDBFD3E2DEBF20E2A0E0B0E201C0CF
:1000C0001D92A830B207E1F735D1B3C199CF8F9215
:1000D0009F92AF92BF92CF92DF92EF92FF920F93D7
:1000E0001F93CF93DF93A0900020B0900120C09089
:1000F0000220D0900320E0900420F0900520009191
:10010000062010910720DC01CB019C01AD0160E0CD
:1001100070E080E090E06FD14901D42FC52FB62F59
:10012000A72FF82FE92FA0900020B0900120C090B9
:100130000220D0900320E0900420F0900520009150
:1001400006201091072094014D2F5C2F6B2F7A2FE2
:100150008F2F9E2F65D119F010F0A895E4CFDF9175
:10016000CF911F910F91FF90EF90DF90CF90BF90B4
:10017000AF909F908F900895CF92DF92EF92FF9271
:100180000F931F93CF93DF936B017C01C0E8D0E006
:100190001FEF1D839CDF01E00E83C701B60197DFCF
:1001A0000D8302E00E83C701B60191DF0D8304E0E9
:1001B0000E83C701B6018BDF0D8308E00E83C701F4
:1001C000B60185DF0D8300E10E83C701B6017FDF35
:1001D0000D8300E20E83C701B60179DF0D8300E4D1
:1001E0000E83C701B60173DF0D8380E88E83C701DC
:1001F000B6016DDF1D83C701B601DF91CF911F915D
:100200000F91FF90EF90DF90CF9061CFCF92DF9270
:10021000EF92FF920F931F93CF93DF936B017C01BB
:10022000C0E8D0E01FEF1D8352DF00E80E83C70156
:10023000B6014DDF0D8300E40E83C701B60147DF31
:100240000D8300E20E83C701B60141DF0D8300E19B
:100250000E83C701B6013BDF0D8308E00E83C701A3
:10026000B60135DF0D8304E00E83C701B6012FDF31
:100270000D8302E00E83C701B60129DF0D8381E003
:100280008E83C701B60123DF1D83C701B601DF914D
:10029000CF911F910F91FF90EF90DF90CF9017CFEC
:1002A0009F92AF92BF92CF92DF92EF92FF920F9305
:1002B0001F93CF93DF936B017C01C0E8D0E0AA24A9
:1002C000AA94AD8204DF81E8B82EBE82C701B601D0
:1002D000FEDEBD8212E41E83C701B601F8DE1D8377
:1002E00004E20E83C701B601F2DE0D8398E1992E78
:1002F0009E82C701B601EBDE9D820E83C701B60167
:10030000E6DE0D831E83C701B601E1DE1D83BE82DA
:10031000C701B601DCDEAD82C701B601DF91CF9126
:100320001F910F91FF90EF90DF90CF90BF90AF9013
:100330009F90CDCE7894109260008FEF80938000D4
:100340008AEA8093840010924700109246008FE260
:10035000809345008AE3809344006AEF70E080E078
:1003600090E00ADF6AEF70E080E090E04FDF6AEF34
:1003700070E080E090E094DFF0CF1F920F920FB614
:100380000F9211242F933F934F935F936F937F931B
:100390008F939F93AF932091002030910120409143
:1003A00002205091032060910420709105208091DB
:1003B000062090910720A1E027D0209300203093C1
:1003C00001204093022050930320609304207093F7
:1003D00005208093062090930720AF919F918F91E5
:1003E0007F916F915F914F913F912F910F900FBE31
:1003F0000F901F9018952A0D3B1D4C1D5D1D6E1D05
:100400007F1D801F911F08950024A7FD00942A0FCF
:10041000301D401D501D601D701D801D901D0895D4
:100420002A153B054C055D056E057F058007910784
:060430000895F894FFCFCF
:00000001FF
This diff is collapsed.
S00D000043546573742E7372656334
S113000055C00000BAC1000061C000005FC000001C
S11300105DC000005BC0000059C0000057C0000074
S113002055C0000053C0000051C000004FC0000084
S11300304DC000004BC0000049C0000047C0000094
S113004045C0000043C0000041C000003FC00000A4
S11300503DC000003BC0000039C0000037C00000B4
S113006035C0000033C0000031C000002FC00000C4
S11300702DC000002BC0000029C0000027C00000D4
S113008025C0000023C0000021C000001FC00000E4
S11300901DC000001BC0000019C0000017C00000F4
S11300A015C0000013C0000011C0000011241FBEC1
S11300B0CFEFCDBFD3E2DEBF20E2A0E0B0E201C0CB
S11300C01D92A830B207E1F735D1B3C199CF8F9211
S11300D09F92AF92BF92CF92DF92EF92FF920F93D3
S11300E01F93CF93DF93A0900020B0900120C09085
S11300F00220D0900320E0900420F090052000918D
S1130100062010910720DC01CB019C01AD0160E0C9
S113011070E080E090E06FD14901D42FC52FB62F55
S1130120A72FF82FE92FA0900020B0900120C090B5
S11301300220D0900320E0900420F090052000914C
S113014006201091072094014D2F5C2F6B2F7A2FDE
S11301508F2F9E2F65D119F010F0A895E4CFDF9171
S1130160CF911F910F91FF90EF90DF90CF90BF90B0
S1130170AF909F908F900895CF92DF92EF92FF926D
S11301800F931F93CF93DF936B017C01C0E8D0E002
S11301901FEF1D839CDF01E00E83C701B60197DFCB
S11301A00D8302E00E83C701B60191DF0D8304E0E5
S11301B00E83C701B6018BDF0D8308E00E83C701F0
S11301C0B60185DF0D8300E10E83C701B6017FDF31
S11301D00D8300E20E83C701B60179DF0D8300E4CD
S11301E00E83C701B60173DF0D8380E88E83C701D8
S11301F0B6016DDF1D83C701B601DF91CF911F9159
S11302000F91FF90EF90DF90CF9061CFCF92DF926C
S1130210EF92FF920F931F93CF93DF936B017C01B7
S1130220C0E8D0E01FEF1D8352DF00E80E83C70152
S1130230B6014DDF0D8300E40E83C701B60147DF2D
S11302400D8300E20E83C701B60141DF0D8300E197
S11302500E83C701B6013BDF0D8308E00E83C7019F
S1130260B60135DF0D8304E00E83C701B6012FDF2D
S11302700D8302E00E83C701B60129DF0D8381E0FF
S11302808E83C701B60123DF1D83C701B601DF9149
S1130290CF911F910F91FF90EF90DF90CF9017CFE8
S11302A09F92AF92BF92CF92DF92EF92FF920F9301
S11302B01F93CF93DF936B017C01C0E8D0E0AA24A5
S11302C0AA94AD8204DF81E8B82EBE82C701B601CC
S11302D0FEDEBD8212E41E83C701B601F8DE1D8373
S11302E004E20E83C701B601F2DE0D8398E1992E74
S11302F09E82C701B601EBDE9D820E83C701B60163
S1130300E6DE0D831E83C701B601E1DE1D83BE82D6
S1130310C701B601DCDEAD82C701B601DF91CF9122
S11303201F910F91FF90EF90DF90CF90BF90AF900F
S11303309F90CDCE7894109260008FEF80938000D0
S11303408AEA8093840010924700109246008FE25C
S1130350809345008AE3809344006AEF70E080E074
S113036090E00ADF6AEF70E080E090E04FDF6AEF30
S113037070E080E090E094DFF0CF1F920F920FB610
S11303800F9211242F933F934F935F936F937F9317
S11303908F939F93AF93209100203091012040913F
S11303A002205091032060910420709105208091D7
S11303B0062090910720A1E027D0209300203093BD
S11303C001204093022050930320609304207093F3
S11303D005208093062090930720AF919F918F91E1
S11303E07F916F915F914F913F912F910F900FBE2D
S11303F00F901F9018952A0D3B1D4C1D5D1D6E1D01
S11304007F1D801F911F08950024A7FD00942A0FCB
S1130410301D401D501D601D701D801D901D0895D0
S11304202A153B054C055D056E057F058007910780
S10904300895F894FFCFCB
S9030000FC
/*
* io_addrs.h
*
* Created: 8/4/2018 22:10:54
* Author: Work
*/
#ifndef IO_DEFS_H_
#define IO_DEFS_H_
#include "xio.h"
#define CPU_FREQ (12090000)
#define UART_INTERFACE_COUNT 0
#define SPI_INTERFACE_COUNT 0
#define TWI_INTERFACE_COUNT 0
#define FPGA_RTC (*(FPGA_RTC_t *) 0x0040) /* Virtual Port */
#define FPGA_PORTA (*(FPGA_PORT_t *) 0x0060) /* Virtual Port */
#define FPGA_PORTB (*(FPGA_PORT_t *) 0x0080) /* Virtual Port */
#define FPGA_PORTC (*(FPGA_PORT_t *) 0x00A0) /* Virtual Port */
#define FPGA_UARTA (*(FPGA_USART_t *) 0x00C0) /* Virtual Port */
#define RTC_vect _VECTOR(1)
#define PORTA_vect _VECTOR(2)
#define PORTB_vect _VECTOR(3)
#define PORTC_vect _VECTOR(4)
#define UART_A_RXC_vect _VECTOR(5)
#define UART_A_TXC_vect _VECTOR(6)
#define UART_A_DRE_vect _VECTOR(7)
#endif /* IO_ADDRS_H_ */
\ No newline at end of file
This diff is collapsed.
# XMEGA_CORE_IP_V2
# On LATTICE MachXOLF is now fully tested and is functional.
This is an optimized IP of the Atmel MEGA and XMEGA processor, that is very simple to use.
The ALU and the muxes are fully asynchronous only the PC is clocked ate positive edge of the clock.
The posedge to posedge clock latency must be bigger than total latency of the ROM memory and core logic.