Commit 96674d9d authored by Iulian Gheorghiu's avatar Iulian Gheorghiu

Initial release

parent 65922659
This diff is collapsed.
[General]
showNCD=true
showPgroups=true
showCongestion=false
showConnsSelect=false
showConnsBetween=true
showConnsOutside=true
showLPF=true
showREGIONs=true
showUGROUPs=true
showPARITIONs=true
showLogicalConnections=false
dontShowBBoxOverlapWarning=false
sceneInViewRect=@Variant(\0\0\0\x14\xc0\xeaJ\xb0`&u\xca\xc0\xa2\x85\x1d>\xe5\xf5\x96\x41\x10\xed\xac\xbb~2{@\xfa\xa9\xef?\xb3\x14p)
[SysIOView]
Type=100
Name=100
Pin=100
Bank=100
IO_TYPE=100
PULLMODE=100
DRIVE=100
SLEWRATE=100
CLAMP=100
OPENDRAIN=100
DIFFRESISTOR=100
DIFFDRIVE=100
BANK_VCCIO=100
HYSTERESIS=100
SortColumns="1,"
[PLLView]
Type=100
Name=100
SortColumns="2,"
[MemoryTreeView]
EBR%20Configuration=314
Setting=1250
[Runmanager]
Geometry=@ByteArray(\x1\xd9\xd0\xcb\0\x1\0\0\0\0\0\0\0\0\0\0\0\0\x1\x1c\0\0\0\xd8\0\0\0\0\0\0\0\0\xff\xff\xff\xff\xff\xff\xff\xff\0\0\0\0\0\0)
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headerState=@ByteArray(\0\0\0\xff\0\0\0\0\0\0\0\x1\0\0\0\x1\0\0\0\0\x1\0\0\0\0\0\0\0\0\0\0\0\x16\0\xe0?\0\0\0\t\0\0\0\x10\0\0\0\x64\0\0\0\xf\0\0\0\x64\0\0\0\xe\0\0\0\x64\0\0\0\r\0\0\0\x64\0\0\0\x15\0\0\0\x64\0\0\0\x14\0\0\0\x64\0\0\0\x13\0\0\0\x64\0\0\0\x12\0\0\0\x64\0\0\0\x11\0\0\0\x64\0\0\x5\xd9\0\0\0\x16\x1\x1\0\x1\0\0\0\0\0\0\0\0\0\0\0\0\x64\xff\xff\xff\xff\0\0\0\x81\0\0\0\0\0\0\0\x4\0\0\0#\0\0\0\x1\0\0\0\x2\0\0\x4L\0\0\0\v\0\0\0\0\0\0\x1j\0\0\0\x1\0\0\0\0\0\0\0\0\0\0\0\t\0\0\0\0)
[impl1%3CStrategy1%3E]
isChecked=true
isHidden=false
isExpanded=false
[General]
Map.auto_tasks=MapTrace, MapVerilogSimFile
PAR.auto_tasks=PARTrace, IOTiming
Export.auto_tasks=TimingSimFileVlg, Bitgen
EnableRealTimePIODRCOnSSV=true
AutoAssign=false
[General]
COLUMN_POS_INFO_NAME_-1_0=Prioritize
COLUMN_POS_INFO_NAME_-1_1=PIO Register
[General]
pin_sort_type=0
pin_sort_ascending=true
sig_sort_type=0
sig_sort_ascending=true
active_Sheet=Port Assignments
[Port%20Assignments]
Name="140,0"
Group%20By="84,1"
Pin="67,2"
BANK="62,3"
BANK_VCC="90,4"
VREF="60,5"
IO_TYPE="147,6"
PULLMODE="97,7"
DRIVE="67,8"
SLEWRATE="92,9"
CLAMP="71,10"
OPENDRAIN="97,11"
DIFFRESISTOR="114,12"
DIFFDRIVE="92,13"
HYSTERESIS="101,14"
Outload%20%28pF%29="103,15"
MaxSkew="87,16"
Clock%20Load%20Only="121,17"
SwitchingID="100,18"
Ground%20plane%20PCB%20noise%20%28mV%29="196,19"
Power%20plane%20PCB%20noise%20%28mV%29="190,20"
SSO%20Allowance%28%25%29="138,21"
sort_columns="DRIVE,Ascending"
[Pin%20Assignments]
Pin="90,0"
Pad%20Name="89,1"
Dual%20Function="261,2"
Polarity="77,3"
BANK="0,4"
BANK_VCC="90,5"
IO_TYPE="147,6"
Signal%20Name="102,7"
Signal%20Type="98,8"
sort_columns="Pin,Ascending"
[Clock%20Resource]
Clock%20Type="100,ELLIPSIS"
Clock%20Name="201,ELLIPSIS"
Selection="100,ELLIPSIS"
[Global%20Preferences]
Preference%20Name="231,ELLIPSIS"
Preference%20Value="236,ELLIPSIS"
[Cell%20Mapping]
Type="100,ELLIPSIS"
Name="100,ELLIPSIS"
Din\Dout="100,ELLIPSIS"
PIO%20Register="100,ELLIPSIS"
[Route%20Priority]
Type="100,ELLIPSIS"
Name="100,ELLIPSIS"
Prioritize="100,ELLIPSIS"
[Timing%20Preferences]
Preference%20Name="138,ELLIPSIS"
Preference%20Value="105,ELLIPSIS"
Preference%20Unit="1250,ELLIPSIS"
[Group]
Group%20Type\Name="134,ELLIPSIS"
Value="1359,ELLIPSIS"
[Misc%20Preferences]
Preference%20Name="117,ELLIPSIS"
Preference%20Value="1376,ELLIPSIS"
# XMEGA_CORE_IP_V2
# On LATTICE MachXOLF is not fully tested (IS NOT FUNCTIONAL).
This is an optimized IP of the Atmel MEGA and XMEGA processor, that is very simple to use.
The ALU and the muxes are fully asynchronous only the PC is clocked ate positive edge of the clock.
The posedge to posedge clock latency must be bigger than total latency of the ROM memory and core logic.
Utilization report from implementation for CORE_TYPE_XMEGA:
|Resource | Utilization | Available | Utilization % |
|:--------|------------:|----------:|--------------:|
|`PFU` | 121 | 6864 | 2 |
|`SLICE` | 1870 | 3432 | 54 |
|`LUT4s` | 3739 | 6864 | 54 |
This results are with two configurable paralel ports, 1KByte of RAM and ~ 512 Bytes of ROM.
The IP was moved to https://git.morgothdisk.com/MorgothCreator/VHDL-UTIL-IP directory, here is only the implementation project with implementation top and simulation top.
More details about instruction set implementation of different core type you can read here: https://en.wikipedia.org/wiki/Atmel_AVR_instruction_set
The core is configurable from minimal core to XMEGA core.
At this moment has implemented the next instructions:
* NOP (1 clock)
* MOVW (1 clock)
* MULS (2 clock) (original 1 clock) One extra clock because is a cascade unit and take longer.
* MULSU (2 clock) (original 1 clock) One extra clock because is a cascade unit and take longer.
* FMUL (2 clock) (original 1 clock) One extra clock because is a cascade unit and take longer.
* FMULS(U) (2 clock) (original 1 clock) One extra clock because is a cascade unit and take longer.
* CPC, CP (1 clock)
* SBC, SUB (1 clock)
* ADD, ADC, ROL, LSL (1 clock)
* CPSE (2 clock)
* AND (1 clock)
* EOR (1 clock)
* OR (1 clock)
* MOV (1 clock)
* CPI (1 clock)
* SBCI, SUBI (1 clock)
* ORI, SBR (1 clock)
* ANDI, CBR (1 clock)
* LDD, STD (1 clock) (original 2 clock)
* LDS, STS (1 clock) (original 2/3 clock)
* LD Y+, LD Z+, ST Y+, ST Z+ (2 clock)
* LD -Y, LD -Z, ST -Y, ST -Z (2 clock)
* LPM_Z (2 clock) (original 3 clock)
* LPM_Z+ (2 clock) (original 3 clock)
* XCH, LAS, LAC, LAT (1 clock) (original 2 clock) (from second revision silicon - AU,B,C parts)
* LD_X, ST_X (1 clock) (original 2 clock)
* LD X+, ST X+ (2 clock)
* LD -X, ST -X (2 clock)
* POP (1 clock) (original 2 clock)
* PUSH (1 clock)
* COM (1 clock)
* NEG (1 clock)
* SWAP (1 clock)
* INC (1 clock)
* ASR (1 clock)
* LSR (1 clock)
* ROR (1 clock)
* SEx, CLx(1 clock)
* RET (2 clock)
* RETI (2 clock)
* IJMP (1 clock) (original 2 clock)
* ICALL (2 clock) (original 3 clock)
* DEC (1 clock)
* JMP, CALL (2 clock) (original 3 clock)
* ADIW (1 clock)
* SBIW (1 clock)
* CBI, SBI (1 clock)
* SBIC, SBIS (2 clock)
* MUL (2 clock) (original 1 clock) One extra clock because is a cascade unit and take longer.
* IN, OUT (1 clock)
* RJMP, RCALL (1 clock, 2 clock)
* LDI (1 clock)
* BRxx (1 clock)
* BLD, BST (1 clock)
* SBRC, SBRS (2 clock)
All instruction that is executed on more than 1 core clock it will be optimized, except multiply that is a cascade unit and take longer for result came on.
The implementation project is made for LATTICE MachXOFL Starter Kit.
On the implementation and simulation it run this bounch of code that will togle and xor the eight LEDs from board with the four switches from the board every several seconds.
The core work at 17Mhz without timing violations, but in reality can work at 20Mhz.
This sequency is made to test some of the implemented instructions.
```c
/*
* CTest.c
*
* Created: 3/13/2018 10:14:25 PM
* Author: Iulian Gheorghiu
*/
#include <avr/io.h>
//#define delay_cycles 0x0000000F
#define delay_cycles 0x01000000
typedef struct PORT_S_struct
{
register8_t PORT_S_DIR; /* I/O Port Data Direction */
register8_t PORT_S_OUT; /* I/O Port Output */
register8_t PORT_S_IN; /* I/O Port Input */
} PORT_S_t;
#define PORTA_S (*(PORT_S_t *)64)
#define PORTB_S (*(PORT_S_t *)68)
#define PORTC_S (*(PORT_S_t *)72)
#define PORTD_S (*(PORT_S_t *)76)
#define PORTE_S (*(PORT_S_t *)80)
#define PORTF_S (*(PORT_S_t *)84)
void delay(unsigned long times)
{
volatile long cnt;
for (cnt = 0; cnt < times; cnt++)
{
;
}
}
int main(void)
{
PORTA_S.PORT_S_DIR = 0;
PORTB_S.PORT_S_DIR = 0xFF;
PORTB_S.PORT_S_OUT = 0x55;
while(1)
{
//TODO:: Please write your application code
delay(delay_cycles);
PORTB_S.PORT_S_OUT = PORTA_S.PORT_S_IN;
delay(delay_cycles);
PORTB_S.PORT_S_OUT = PORTA_S.PORT_S_IN ^ 0xFF;
}
}
```
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<?xml version="1.0" encoding="UTF-8"?>
<BaliProject version="3.2" title="XmegaCoreIpTstLattice" device="LCMXO3LF-6900C-5BG256C" default_implementation="impl1">
<Options/>
<Implementation title="impl1" dir="impl1" description="impl1" synthesis="lse" default_strategy="Strategy1">
<Options def_top="top_uc" top="top_uc"/>
<Source name="../VHDL-UTIL-IP/xmega_core/sim_uc.v" type="Verilog" type_short="Verilog">
<Options/>
</Source>
<Source name="../VHDL-UTIL-IP/xmega_core/io/io.v" type="Verilog" type_short="Verilog">
<Options/>
</Source>
<Source name="../VHDL-UTIL-IP/xmega_core/io/io_i2c.v" type="Verilog" type_short="Verilog">
<Options/>
</Source>
<Source name="../VHDL-UTIL-IP/xmega_core/io/io_s_h.v" type="Verilog" type_short="Verilog">
<Options/>
</Source>
<Source name="../VHDL-UTIL-IP/xmega_core/io/io_spi.v" type="Verilog" type_short="Verilog">
<Options/>
</Source>
<Source name="../VHDL-UTIL-IP/xmega_core/io/io_uart.v" type="Verilog" type_short="Verilog">
<Options/>
</Source>
<Source name="../VHDL-UTIL-IP/xmega_core/io/pio.v" type="Verilog" type_short="Verilog">
<Options/>
</Source>
<Source name="../VHDL-UTIL-IP/xmega_core/io/pio_s.v" type="Verilog" type_short="Verilog">
<Options/>
</Source>
<Source name="top_uc.v" type="Verilog" type_short="Verilog">
<Options top_module="top_uc"/>
</Source>
<Source name="../VHDL-UTIL-IP/xmega_core/mega_core_opt.v" type="Verilog" type_short="Verilog">
<Options/>
</Source>
<Source name="../VHDL-UTIL-IP/memory.v" type="Verilog" type_short="Verilog">
<Options/>
</Source>
<Source name="core1ROM.mem" type="Unknown Type" type_short="Unknown">
<Options/>
</Source>
<Source name="impl1/impl1.xcf" type="Programming Project File" type_short="Programming">
<Options/>
</Source>
<Source name="sim/sim.spf" type="Simulation Project File" type_short="SPF">
<Options/>
</Source>
<Source name="untitled.rva" type="Reveal Analyzer Project File" type_short="RVA">
<Options/>
</Source>
<Source name="xmega.rvl" type="Reveal" type_short="Reveal">
<Options/>
</Source>
<Source name="XmegaCoreIpTstLattice.lpf" type="Logic Preference" type_short="LPF">
<Options/>
</Source>
</Implementation>
<Strategy name="Strategy1" file="XmegaCoreIpTstLattice1.sty"/>
</BaliProject>
rvl_alias "core_clk" "rom_inst/clk";
RVL_ALIAS "core_clk" "rom_inst/clk";
BLOCK RESETPATHS ;
BLOCK ASYNCPATHS ;
IOBUF PORT "btn[0]" IO_TYPE=LVCMOS33 ;
IOBUF PORT "btn[1]" IO_TYPE=LVCMOS33 ;
IOBUF PORT "btn[2]" IO_TYPE=LVCMOS33 ;
IOBUF PORT "btn[3]" IO_TYPE=LVCMOS33 ;
IOBUF PORT "leds[0]" IO_TYPE=LVCMOS33 ;
IOBUF PORT "leds[1]" IO_TYPE=LVCMOS33 ;
IOBUF PORT "leds[2]" IO_TYPE=LVCMOS33 ;
IOBUF PORT "leds[3]" IO_TYPE=LVCMOS33 ;
IOBUF PORT "leds[4]" IO_TYPE=LVCMOS33 ;
IOBUF PORT "leds[5]" IO_TYPE=LVCMOS33 ;
IOBUF PORT "leds[6]" IO_TYPE=LVCMOS33 ;
IOBUF PORT "leds[7]" IO_TYPE=LVCMOS33 ;
LOCATE COMP "btn[0]" SITE "N2" ;
LOCATE COMP "leds[0]" SITE "P16" ;
LOCATE COMP "leds[1]" SITE "N15" ;
LOCATE COMP "leds[2]" SITE "L13" ;
LOCATE COMP "leds[3]" SITE "K11" ;
LOCATE COMP "leds[4]" SITE "L12" ;
LOCATE COMP "leds[5]" SITE "J11" ;
LOCATE COMP "leds[6]" SITE "J13" ;
LOCATE COMP "leds[7]" SITE "H11" ;
LOCATE COMP "btn[1]" SITE "P1" ;
LOCATE COMP "btn[2]" SITE "M3" ;
LOCATE COMP "btn[3]" SITE "N1" ;
IOBUF PORT "btn_rst" IO_TYPE=LVCMOS33 DRIVE=NA SLEWRATE=NA CLAMP=ON HYSTERESIS=LARGE ;
LOCATE COMP "btn_rst" SITE "B3" ;
BLOCK JTAGPATHS ;
This diff is collapsed.
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<PRE><A name="pn180616151958"></A><B><U><big>pn180616151958</big></U></B>
#Start recording tcl command: 6/16/2018 14:57:16
#Project Location: C:/GitHub/XMEGA-CORE-IP-TST-LATTICE; Project name: XmegaCoreIpTstLattice
prj_project open "C:/GitHub/XMEGA-CORE-IP-TST-LATTICE/XmegaCoreIpTstLattice.ldf"
#Stop recording: 6/16/2018 15:19:58
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#Start recording tcl command: 6/16/2018 14:57:16
#Project Location: C:/GitHub/XMEGA-CORE-IP-TST-LATTICE; Project name: XmegaCoreIpTstLattice
prj_project open "C:/GitHub/XMEGA-CORE-IP-TST-LATTICE/XmegaCoreIpTstLattice.ldf"
#Stop recording: 6/16/2018 15:19:58
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