Commit 7079a1d9 authored by Iulian Gheorghiu's avatar Iulian Gheorghiu

Fix some issues

parent 48d440a9
......@@ -11,4 +11,4 @@ showUGROUPs=true
showPARITIONs=true
showLogicalConnections=false
dontShowBBoxOverlapWarning=false
sceneInViewRect=@Variant(\0\0\0\x14\xc1\x15\xf6\x8e\x9c\x16\x9f\x1b\xc1\nGm&\x14[\xff\x41+*\x89\xd3\x82\xd3\xe4\x41 Z:\x1b\xe6\\\xc0)
sceneInViewRect="@Variant(\0\0\0\x14\xc1\x16\x15\x90O,\xdd\xb1\xc1\nqz\xd2\x61\x45\xc0\x41+IC\xbf\xe7\xde\xd2\x41 l\xb8\xef\xc9\xb5Z)"
......@@ -2,7 +2,7 @@
<BaliProject version="3.2" title="XmegaCoreIpTstLattice" device="LCMXO3LF-6900C-5BG256C" default_implementation="impl1">
<Options/>
<Implementation title="impl1" dir="impl1" description="impl1" synthesis="lse" default_strategy="Strategy1">
<Options top="top_uc"/>
<Options def_top="sim_uc" top="top_uc"/>
<Source name="top_uc.v" type="Verilog" type_short="Verilog">
<Options top_module="top_uc"/>
</Source>
......
......@@ -3,50 +3,50 @@
<Strategy name="Strategy1">
<Milestone name="Export" build_result="0" build_time="0">
<Task name="IBIS" build_result="0" update_result="2" update_time="1528969056"/>
<Task name="TimingSimFileVlg" build_result="2" update_result="0" update_time="1539266269"/>
<Task name="TimingSimFileVlg" build_result="2" update_result="0" update_time="1539269216"/>
<Task name="TimingSimFileVHD" build_result="0" update_result="3" update_time="0"/>
<Task name="Bitgen" build_result="2" update_result="0" update_time="1539266273"/>
<Task name="Jedecgen" build_result="2" update_result="0" update_time="1539266277"/>
<Task name="Bitgen" build_result="2" update_result="0" update_time="1539269219"/>
<Task name="Jedecgen" build_result="2" update_result="0" update_time="1539269223"/>
<Task name="Jedec4Xo3l" build_result="0" update_result="3" update_time="0"/>
<Task name="Bitgen4Xo3l" build_result="0" update_result="3" update_time="0"/>
</Milestone>
<Milestone name="Map" build_result="2" build_time="1539266152">
<Task name="Map" build_result="2" update_result="0" update_time="1539266152"/>
<Task name="MapTrace" build_result="2" update_result="0" update_time="1539266154"/>
<Task name="MapVerilogSimFile" build_result="2" update_result="0" update_time="1539266158"/>
<Milestone name="Map" build_result="2" build_time="1539269118">
<Task name="Map" build_result="2" update_result="0" update_time="1539269118"/>
<Task name="MapTrace" build_result="2" update_result="0" update_time="1539269119"/>
<Task name="MapVerilogSimFile" build_result="2" update_result="0" update_time="1539269123"/>
<Task name="MapVHDLSimFile" build_result="0" update_result="3" update_time="0"/>
</Milestone>
<Milestone name="PAR" build_result="2" build_time="1539266259">
<Task name="PAR" build_result="2" update_result="0" update_time="1539266259"/>
<Task name="PARTrace" build_result="2" update_result="0" update_time="1539266260"/>
<Task name="IOTiming" build_result="2" update_result="0" update_time="1539266264"/>
<Milestone name="PAR" build_result="2" build_time="1539269205">
<Task name="PAR" build_result="2" update_result="0" update_time="1539269205"/>
<Task name="PARTrace" build_result="2" update_result="0" update_time="1539269207"/>
<Task name="IOTiming" build_result="2" update_result="0" update_time="1539269211"/>
</Milestone>
<Milestone name="Synthesis" build_result="2" build_time="1539266150">
<Task name="Lattice_Synthesis" build_result="2" update_result="0" update_time="1539266150"/>
<Task name="LSE_Compile" build_result="2" update_result="0" update_time="1539266277"/>
<Milestone name="Synthesis" build_result="2" build_time="1539269115">
<Task name="Lattice_Synthesis" build_result="2" update_result="0" update_time="1539269115"/>
<Task name="LSE_Compile" build_result="2" update_result="0" update_time="1539269223"/>
</Milestone>
<Milestone name="TOOL_Report" build_result="0" build_time="0">
<Task name="HDLE" build_result="0" update_result="2" update_time="1539256154"/>
<Task name="HDLE" build_result="2" update_result="0" update_time="1539268916"/>
<Task name="DEC" build_result="0" update_result="2" update_time="0"/>
<Task name="SSO" build_result="0" update_result="2" update_time="1528979648"/>
<Task name="PIODRC" build_result="0" update_result="2" update_time="0"/>
<Task name="BKM" build_result="0" update_result="2" update_time="0"/>
</Milestone>
<Report name=".vdbs/XmegaCoreIpTstLattice_impl1_map.vdb" last_build_time="1539266152" last_build_size="670715"/>
<Report name=".vdbs/XmegaCoreIpTstLattice_impl1_map.vdb" last_build_time="1539269118" last_build_size="688739"/>
<Report name="IBIS/XmegaCoreIpTstLattice_impl1.ibs" last_build_time="1528969056" last_build_size="17519"/>
<Report name="XmegaCoreIpTstLattice_impl1.bgn" last_build_time="1539266276" last_build_size="4461"/>
<Report name="XmegaCoreIpTstLattice_impl1.bit" last_build_time="1539266273" last_build_size="65040"/>
<Report name="XmegaCoreIpTstLattice_impl1.ior" last_build_time="1539266264" last_build_size="2385"/>
<Report name="XmegaCoreIpTstLattice_impl1.jed" last_build_time="1539266276" last_build_size="1464855"/>
<Report name="XmegaCoreIpTstLattice_impl1.lsedata" last_build_time="1539265995" last_build_size="3123263"/>
<Report name="XmegaCoreIpTstLattice_impl1.ncd" last_build_time="1539266259" last_build_size="3279506"/>
<Report name="XmegaCoreIpTstLattice_impl1.ngd" last_build_time="1539266149" last_build_size="2208806"/>
<Report name="XmegaCoreIpTstLattice_impl1.tw1" last_build_time="1539266154" last_build_size="38871"/>
<Report name="XmegaCoreIpTstLattice_impl1.twr" last_build_time="1539266260" last_build_size="184445"/>
<Report name="XmegaCoreIpTstLattice_impl1_map.ncd" last_build_time="1539266152" last_build_size="2124423"/>
<Report name="XmegaCoreIpTstLattice_impl1_mapvo.sdf" last_build_time="1539266158" last_build_size="2696491"/>
<Report name="XmegaCoreIpTstLattice_impl1_mapvo.vo" last_build_time="1539266157" last_build_size="2537231"/>
<Report name="XmegaCoreIpTstLattice_impl1_vo.sdf" last_build_time="1539266269" last_build_size="2961766"/>
<Report name="XmegaCoreIpTstLattice_impl1_vo.vo" last_build_time="1539266268" last_build_size="2723483"/>
<Report name="XmegaCoreIpTstLattice_impl1.bgn" last_build_time="1539269223" last_build_size="4461"/>
<Report name="XmegaCoreIpTstLattice_impl1.bit" last_build_time="1539269219" last_build_size="64618"/>
<Report name="XmegaCoreIpTstLattice_impl1.ior" last_build_time="1539269211" last_build_size="2385"/>
<Report name="XmegaCoreIpTstLattice_impl1.jed" last_build_time="1539269223" last_build_size="1464855"/>
<Report name="XmegaCoreIpTstLattice_impl1.lsedata" last_build_time="1539268957" last_build_size="3123158"/>
<Report name="XmegaCoreIpTstLattice_impl1.ncd" last_build_time="1539269205" last_build_size="3290023"/>
<Report name="XmegaCoreIpTstLattice_impl1.ngd" last_build_time="1539269115" last_build_size="2219911"/>
<Report name="XmegaCoreIpTstLattice_impl1.tw1" last_build_time="1539269119" last_build_size="37952"/>
<Report name="XmegaCoreIpTstLattice_impl1.twr" last_build_time="1539269207" last_build_size="162662"/>
<Report name="XmegaCoreIpTstLattice_impl1_map.ncd" last_build_time="1539269117" last_build_size="2141004"/>
<Report name="XmegaCoreIpTstLattice_impl1_mapvo.sdf" last_build_time="1539269123" last_build_size="2712074"/>
<Report name="XmegaCoreIpTstLattice_impl1_mapvo.vo" last_build_time="1539269123" last_build_size="2557082"/>
<Report name="XmegaCoreIpTstLattice_impl1_vo.sdf" last_build_time="1539269215" last_build_size="2977360"/>
<Report name="XmegaCoreIpTstLattice_impl1_vo.vo" last_build_time="1539269215" last_build_size="2741337"/>
</Strategy>
</BuildStatus>
NOTE Copyright (C), 1992-2010, Lattice Semiconductor Corporation *
NOTE All Rights Reserved *
NOTE DATE CREATED: Thu Oct 11 16:57:56 2018 *
NOTE DATE CREATED: Thu Oct 11 17:47:03 2018 *
NOTE DESIGN NAME: top_uc *
NOTE DEVICE NAME: LCMXO3LF-6900C-5CABGA256 *
NOTE PIN ASSIGNMENTS *
......
This diff is collapsed.
......@@ -6,7 +6,7 @@ Performance Grade: 5
PACKAGE: CABGA256
Package Status: Final Version 1.16
Thu Oct 11 16:57:10 2018
Thu Oct 11 17:45:46 2018
Pinout by Port Name:
+-----------+----------+---------------+-------+-----------+-----------+----------------------------------------------------------+
......@@ -424,5 +424,5 @@ Copyright (c) 1995 AT&T Corp. All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
Copyright (c) 2001 Agere Systems All rights reserved.
Copyright (c) 2002-2017 Lattice Semiconductor Corporation, All rights reserved.
Thu Oct 11 16:57:10 2018
Thu Oct 11 17:45:46 2018
......@@ -4,39 +4,34 @@ GLOBAL_PRIMARY_USED = 1;
; Global primary clock #0
GLOBAL_PRIMARY_0_SIGNALNAME = core_clk;
GLOBAL_PRIMARY_0_DRIVERTYPE = OSC;
GLOBAL_PRIMARY_0_LOADNUM = 199;
GLOBAL_PRIMARY_0_LOADNUM = 195;
; # of global secondary clocks
GLOBAL_SECONDARY_USED = 6;
GLOBAL_SECONDARY_USED = 5;
; Global secondary clock #0
GLOBAL_SECONDARY_0_SIGNALNAME = btn_rst_c;
GLOBAL_SECONDARY_0_DRIVERTYPE = PIO;
GLOBAL_SECONDARY_0_LOADNUM = 19;
GLOBAL_SECONDARY_0_SIGTYPE = RST;
; Global secondary clock #1
GLOBAL_SECONDARY_1_SIGNALNAME = pgm_addr_12__I_0/n3279369;
GLOBAL_SECONDARY_1_SIGNALNAME = pgm_addr_12__I_0/n3280533;
GLOBAL_SECONDARY_1_DRIVERTYPE = SLICE;
GLOBAL_SECONDARY_1_LOADNUM = 49;
GLOBAL_SECONDARY_1_LOADNUM = 50;
GLOBAL_SECONDARY_1_SIGTYPE = RST;
; Global secondary clock #2
GLOBAL_SECONDARY_2_SIGNALNAME = pgm_addr_12__I_0/core_clk_enable_21;
GLOBAL_SECONDARY_2_SIGNALNAME = pgm_addr_12__I_0/core_clk_enable_249;
GLOBAL_SECONDARY_2_DRIVERTYPE = SLICE;
GLOBAL_SECONDARY_2_LOADNUM = 13;
GLOBAL_SECONDARY_2_LOADNUM = 24;
GLOBAL_SECONDARY_2_SIGTYPE = CE;
; Global secondary clock #3
GLOBAL_SECONDARY_3_SIGNALNAME = pgm_addr_12__I_0/core_clk_enable_249;
GLOBAL_SECONDARY_3_SIGNALNAME = pgm_addr_12__I_0/wdt_inst/core_clk_enable_259;
GLOBAL_SECONDARY_3_DRIVERTYPE = SLICE;
GLOBAL_SECONDARY_3_LOADNUM = 24;
GLOBAL_SECONDARY_3_LOADNUM = 14;
GLOBAL_SECONDARY_3_SIGTYPE = CE;
; Global secondary clock #4
GLOBAL_SECONDARY_4_SIGNALNAME = pgm_addr_12__I_0/wdt_inst/core_clk_enable_260;
GLOBAL_SECONDARY_4_SIGNALNAME = rtc/core_clk_enable_256;
GLOBAL_SECONDARY_4_DRIVERTYPE = SLICE;
GLOBAL_SECONDARY_4_LOADNUM = 14;
GLOBAL_SECONDARY_4_LOADNUM = 16;
GLOBAL_SECONDARY_4_SIGTYPE = CE;
; Global secondary clock #5
GLOBAL_SECONDARY_5_SIGNALNAME = rtc/core_clk_enable_256;
GLOBAL_SECONDARY_5_DRIVERTYPE = SLICE;
GLOBAL_SECONDARY_5_LOADNUM = 16;
GLOBAL_SECONDARY_5_SIGTYPE = CE;
; I/O Bank 0 Usage
BANK_0_USED = 1;
BANK_0_AVAIL = 51;
......
......@@ -4,13 +4,13 @@ GLOBAL_PRIMARY_USED = 1;
; Global primary clock #0
GLOBAL_PRIMARY_0_SIGNALNAME = core_clk;
GLOBAL_PRIMARY_0_DRIVERTYPE = OSC;
GLOBAL_PRIMARY_0_LOADNUM = 199;
GLOBAL_PRIMARY_0_LOADNUM = 195;
; # of global secondary clocks
GLOBAL_SECONDARY_USED = 6;
GLOBAL_SECONDARY_USED = 5;
; Global secondary clock #0
GLOBAL_SECONDARY_0_SIGNALNAME = pgm_addr_12__I_0/core_clk_enable_21;
GLOBAL_SECONDARY_0_SIGNALNAME = pgm_addr_12__I_0/core_clk_enable_249;
GLOBAL_SECONDARY_0_DRIVERTYPE = SLICE;
GLOBAL_SECONDARY_0_LOADNUM = 13;
GLOBAL_SECONDARY_0_LOADNUM = 24;
GLOBAL_SECONDARY_0_SIGTYPE = CE;
; Global secondary clock #1
GLOBAL_SECONDARY_1_SIGNALNAME = btn_rst_c;
......@@ -18,25 +18,20 @@ GLOBAL_SECONDARY_1_DRIVERTYPE = PIO;
GLOBAL_SECONDARY_1_LOADNUM = 19;
GLOBAL_SECONDARY_1_SIGTYPE = RST;
; Global secondary clock #2
GLOBAL_SECONDARY_2_SIGNALNAME = pgm_addr_12__I_0/n3279369;
GLOBAL_SECONDARY_2_SIGNALNAME = pgm_addr_12__I_0/n3280533;
GLOBAL_SECONDARY_2_DRIVERTYPE = SLICE;
GLOBAL_SECONDARY_2_LOADNUM = 49;
GLOBAL_SECONDARY_2_LOADNUM = 50;
GLOBAL_SECONDARY_2_SIGTYPE = RST;
; Global secondary clock #3
GLOBAL_SECONDARY_3_SIGNALNAME = pgm_addr_12__I_0/core_clk_enable_249;
GLOBAL_SECONDARY_3_SIGNALNAME = rtc/core_clk_enable_256;
GLOBAL_SECONDARY_3_DRIVERTYPE = SLICE;
GLOBAL_SECONDARY_3_LOADNUM = 24;
GLOBAL_SECONDARY_3_LOADNUM = 16;
GLOBAL_SECONDARY_3_SIGTYPE = CE;
; Global secondary clock #4
GLOBAL_SECONDARY_4_SIGNALNAME = rtc/core_clk_enable_256;
GLOBAL_SECONDARY_4_SIGNALNAME = pgm_addr_12__I_0/wdt_inst/core_clk_enable_259;
GLOBAL_SECONDARY_4_DRIVERTYPE = SLICE;
GLOBAL_SECONDARY_4_LOADNUM = 16;
GLOBAL_SECONDARY_4_LOADNUM = 14;
GLOBAL_SECONDARY_4_SIGTYPE = CE;
; Global secondary clock #5
GLOBAL_SECONDARY_5_SIGNALNAME = pgm_addr_12__I_0/wdt_inst/core_clk_enable_260;
GLOBAL_SECONDARY_5_DRIVERTYPE = SLICE;
GLOBAL_SECONDARY_5_LOADNUM = 14;
GLOBAL_SECONDARY_5_SIGTYPE = CE;
; I/O Bank 0 Usage
BANK_0_USED = 1;
BANK_0_AVAIL = 51;
......
......@@ -4,7 +4,7 @@ Copyright (c) 1995 AT&T Corp. All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
Copyright (c) 2001 Agere Systems All rights reserved.
Copyright (c) 2002-2017 Lattice Semiconductor Corporation, All rights reserved.
Thu Oct 11 16:55:58 2018
Thu Oct 11 17:45:24 2018
C:/lscc/diamond/3.10_x64/ispfpga\bin\nt64\par -f
XmegaCoreIpTstLattice_impl1.p2t XmegaCoreIpTstLattice_impl1_map.ncd
......@@ -17,11 +17,13 @@ Preference file: XmegaCoreIpTstLattice_impl1.prf.
Level/ Number Worst Timing Worst Timing Run NCD
Cost [ncd] Unrouted Slack Score Slack(hold) Score(hold) Time Status
---------- -------- ----- ------ ----------- ----------- ---- ------
5_2 * 0 -3.800 11347897 0.306 0 51 Success
5_1 0 -6.643 22536131 0.306 0 50 Success
5_1 * 0 0.740 0 0.306 0 46 Success
5_2 - - - - - 35 Skipped
* : Design saved.
Total (real) run time for 2-seed: 1 mins 41 secs
INFO - par: Iteration 5_2 was skipped during the PAR process to save total runtime, as it was determined it would not improve upon a timing result achieved in a previous iteration.
Total (real) run time for 2-seed: 1 mins 21 secs
par done!
This diff is collapsed.
......@@ -5193,7 +5193,7 @@
</pins>
<nets>
<nitem name = "int_pio_b" />
<nitem name = "int_pio_a" />
<nitem name = "pio_port_A/pwr" />
<nitem name = "data_addr[13]" />
<nitem name = "data_addr[12]" />
......@@ -5248,7 +5248,7 @@
</pins>
<nets>
<nitem name = "int_pio_b" />
<nitem name = "int_pio_a" />
<nitem name = "pio_port_A/pwr" />
<nitem name = "data_addr[13]" />
<nitem name = "data_addr[12]" />
......@@ -5734,7 +5734,7 @@
</pins>
<nets>
<nitem name = "int_pio_b" />
<nitem name = "int_pio_a" />
<nitem name = "pio_port_A/pwr" />
<nitem name = "data_addr[4]" />
<nitem name = "data_addr[3]" />
......@@ -6411,7 +6411,7 @@
</pins>
<nets>
<nitem name = "int_pio_b" />
<nitem name = "int_pio_a" />
<nitem name = "pio_port_A/wr_int" />
<nitem name = "pio_port_A/PINCTRL_N_417" />
<nitem name = "pio_port_A/PINCTRL_N_416" />
......@@ -6572,7 +6572,7 @@
</pins>
<nets>
<nitem name = "int_pio_b" />
<nitem name = "int_pio_a" />
<nitem name = "sys_rst" />
<nitem name = "core_clk" />
<nitem name = "pio_port_A/IO_OUT[7]" />
......@@ -6645,7 +6645,7 @@
</pins>
<nets>
<nitem name = "int_pio_b" />
<nitem name = "int_pio_a" />
<nitem name = "sys_rst" />
<nitem name = "pio_port_A/PINCTRL_N_415" />
<nitem name = "pio_port_A/PINCTRL_N_416" />
......@@ -6697,7 +6697,7 @@
</pins>
<nets>
<nitem name = "int_pio_b" />
<nitem name = "int_pio_a" />
<nitem name = "pio_port_A/IO_DIR[7]" />
<nitem name = "pio_port_A/IO_DIR[6]" />
<nitem name = "pio_port_A/IO_DIR[5]" />
......@@ -7031,7 +7031,7 @@
</pins>
<nets>
<nitem name = "int_pio_b" />
<nitem name = "int_pio_a" />
<nitem name = "data_addr[4]" />
<nitem name = "data_addr[3]" />
<nitem name = "data_addr[2]" />
......@@ -7234,7 +7234,7 @@
</pins>
<nets>
<nitem name = "int_pio_b" />
<nitem name = "int_pio_a" />
<nitem name = "sys_rst" />
<nitem name = "core_clk" />
<nitem name = "pio_port_A/IO_DIR[7]" />
......@@ -7291,7 +7291,7 @@
</pins>
<nets>
<nitem name = "pio_port_B/n305" />
<nitem name = "int_pio_b" />
<nitem name = "pio_port_B/pwr" />
<nitem name = "data_addr[13]" />
<nitem name = "data_addr[12]" />
......@@ -7346,7 +7346,7 @@
</pins>
<nets>
<nitem name = "pio_port_B/n305" />
<nitem name = "int_pio_b" />
<nitem name = "pio_port_B/pwr" />
<nitem name = "data_addr[13]" />
<nitem name = "data_addr[12]" />
......@@ -7832,7 +7832,7 @@
</pins>
<nets>
<nitem name = "pio_port_B/n305" />
<nitem name = "int_pio_b" />
<nitem name = "pio_port_B/pwr" />
<nitem name = "data_addr[4]" />
<nitem name = "data_addr[3]" />
......@@ -8509,7 +8509,7 @@
</pins>
<nets>
<nitem name = "pio_port_B/n305" />
<nitem name = "int_pio_b" />
<nitem name = "pio_port_B/wr_int" />
<nitem name = "pio_port_B/PINCTRL_N_478" />
<nitem name = "pio_port_B/PINCTRL_N_477" />
......@@ -8670,7 +8670,7 @@
</pins>
<nets>
<nitem name = "pio_port_B/n305" />
<nitem name = "int_pio_b" />
<nitem name = "sys_rst" />
<nitem name = "core_clk" />
<nitem name = "pio_port_B/IO_OUT[7]" />
......@@ -8743,7 +8743,7 @@
</pins>
<nets>
<nitem name = "pio_port_B/n305" />
<nitem name = "int_pio_b" />
<nitem name = "sys_rst" />
<nitem name = "pio_port_B/PINCTRL_N_476" />
<nitem name = "pio_port_B/PINCTRL_N_477" />
......@@ -8795,7 +8795,7 @@
</pins>
<nets>
<nitem name = "pio_port_B/n305" />
<nitem name = "int_pio_b" />
<nitem name = "pio_port_B/IO_DIR[7]" />
<nitem name = "pio_port_B/IO_DIR[6]" />
<nitem name = "pio_port_B/IO_DIR[5]" />
......@@ -9129,7 +9129,7 @@
</pins>
<nets>
<nitem name = "pio_port_B/n305" />
<nitem name = "int_pio_b" />
<nitem name = "data_addr[4]" />
<nitem name = "data_addr[3]" />
<nitem name = "data_addr[2]" />
......@@ -9336,7 +9336,7 @@
</pins>
<nets>
<nitem name = "pio_port_B/n305" />
<nitem name = "int_pio_b" />
<nitem name = "sys_rst" />
<nitem name = "core_clk" />
<nitem name = "pio_port_B/IO_DIR[7]" />
......@@ -44989,7 +44989,7 @@
<nets>
<nitem name = "int_rst[2]" />
<nitem name = "pgm_addr_12__I_0/int_rst[1]" />
<nitem name = "int_rst[1]" />
<nitem name = "int_rst[0]" />
<nitem name = "pgm_addr_12__I_0/alu_rdy_N_861" />
<nitem name = "pgm_addr_12__I_0/n3942" />
......@@ -46120,7 +46120,7 @@
<nets>
<nitem name = "sys_rst" />
<nitem name = "int_rst[2]" />
<nitem name = "pgm_addr_12__I_0/int_rst[1]" />
<nitem name = "int_rst[1]" />
<nitem name = "int_rst[0]" />
<nitem name = "pgm_addr_12__I_0/int_rst_2__N_1282[2]" />
<nitem name = "pgm_addr_12__I_0/int_rst_2__N_1282[1]" />
......@@ -47250,7 +47250,7 @@
<nitem name = "pgm_addr_12__I_0/n3296" />
<nitem name = "core_clk" />
<nitem name = "int_rst[2]" />
<nitem name = "pgm_addr_12__I_0/int_rst[1]" />
<nitem name = "int_rst[1]" />
<nitem name = "int_rst[0]" />
<nitem name = "pgm_addr_12__I_0/int_rst_2__N_870[2]" />
<nitem name = "pgm_addr_12__I_0/int_rst_2__N_870[1]" />
This diff is collapsed.
......@@ -6,7 +6,7 @@ Performance Grade: 5
PACKAGE: CABGA256
Package Status: Final Version 1.16
Thu Oct 11 16:57:10 2018
Thu Oct 11 17:45:46 2018
Pinout by Port Name:
+-----------+----------+---------------+-------+-----------+-----------+----------------------------------------------------------+
......@@ -424,5 +424,5 @@ Copyright (c) 1995 AT&T Corp. All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
Copyright (c) 2001 Agere Systems All rights reserved.
Copyright (c) 2002-2017 Lattice Semiconductor Corporation, All rights reserved.
Thu Oct 11 16:57:10 2018
Thu Oct 11 17:45:46 2018
This diff is collapsed.
SCHEMATIC START ;
# map: version Diamond (64-bit) 3.10.2.115 -- WARNING: Map write only section -- Thu Oct 11 16:55:52 2018
# map: version Diamond (64-bit) 3.10.2.115 -- WARNING: Map write only section -- Thu Oct 11 17:45:17 2018
SYSCONFIG SDM_PORT=DISABLE SLAVE_SPI_PORT=DISABLE I2C_PORT=DISABLE MASTER_SPI_PORT=DISABLE COMPRESS_CONFIG=ON CONFIGURATION=CFG MY_ASSP=OFF ONE_TIME_PROGRAM=OFF CONFIG_SECURE=OFF MCCLK_FREQ=2.08 JTAG_PORT=ENABLE ENABLE_TRANSFR=DISABLE SHAREDEBRINIT=DISABLE MUX_CONFIGURATION_PORTS=DISABLE DUALBOOTGOLDEN=INTERNAL BACKGROUND_RECONFIG=OFF INBUF=ON ;
LOCATE COMP "btn_rst" SITE "B3" ;
......
This diff is collapsed.
This diff is collapsed.
......@@ -29,7 +29,7 @@ Performance Hardware Data Status: Final Version 37.4.
// Package: CABGA256
// ncd File: xmegacoreiptstlattice_impl1.ncd
// Version: Diamond (64-bit) 3.10.2.115
// Written on Thu Oct 11 16:57:44 2018
// Written on Thu Oct 11 17:46:51 2018
// M: Minimum Performance Grade
// iotiming XmegaCoreIpTstLattice_impl1.ncd XmegaCoreIpTstLattice_impl1.prf -gui -msgset C:/GitHub/VERILOG-XMEGA-CORE-IP-TST-LATTICE/promote.xml
......
......@@ -3,9 +3,9 @@ Device = LCMXO3LF-6900C;
Package = CABGA256;
Performance = 5;
LUTS_avail = 6864;
LUTS_used = 3481;
LUTS_used = 3506;
FF_avail = 7071;
FF_used = 302;
FF_used = 299;
INPUT_LVCMOS33 = 1;
BIDI_LVCMOS33 = 12;
IO_avail = 207;
......
[ START MERGED ]
core_clk_enable_250 n3282558
core_clk_enable_250 pgm_addr_12__I_0/sys_rst
btn_rst_N_2 btn_rst_c
n3236206 pio_port_B/IO_DIR_0
n3236204 pio_port_B/IO_DIR_1
n3236202 pio_port_B/IO_DIR_2
n3236200 pio_port_B/IO_DIR_3
n3236198 pio_port_B/IO_DIR_4
n3236196 pio_port_B/IO_DIR_5
n3236194 pio_port_B/IO_DIR_6
n3236192 pio_port_B/IO_DIR_7
n3236203 pio_port_B/IO_DIR_0
n3236201 pio_port_B/IO_DIR_1
n3236199 pio_port_B/IO_DIR_2
n3236197 pio_port_B/IO_DIR_3
n3236195 pio_port_B/IO_DIR_4
n3236193 pio_port_B/IO_DIR_5
n3236191 pio_port_B/IO_DIR_6
n3236189 pio_port_B/IO_DIR_7
[ END MERGED ]
[ START CLIPPED ]
GND_net
VCC_net
rtc/add_18_1/S0
rtc/add_18_1/CI
rtc/sub_3689_add_2_27/S1
rtc/sub_3689_add_2_27/S0
rtc/sub_3689_add_2_29/S1
rtc/sub_3689_add_2_29/S0
rtc/sub_3689_add_2_31/S1
rtc/sub_3689_add_2_31/S0
rtc/sub_3689_add_2_33/S0
rtc/sub_3689_add_2_33/CO
rtc/sub_13_add_2_1/S0
rtc/sub_13_add_2_1/CI
rtc/add_18_33/S1
rtc/add_18_33/CO
rtc/sub_3686_add_2_27/S1
rtc/sub_3686_add_2_27/S0
rtc/sub_3686_add_2_29/S1
rtc/sub_3686_add_2_29/S0
rtc/sub_3686_add_2_31/S1
rtc/sub_3686_add_2_31/S0
rtc/sub_3686_add_2_33/S0
rtc/sub_3686_add_2_33/CO
rtc/sub_13_add_2_33/S1
rtc/sub_13_add_2_33/CO
rtc/sub_3689_add_2_1/S1
rtc/sub_3689_add_2_1/S0
rtc/sub_3689_add_2_1/CI
rtc/sub_3689_add_2_3/S1
rtc/sub_3689_add_2_3/S0
rtc/sub_3689_add_2_5/S1
rtc/sub_3689_add_2_5/S0
rtc/sub_3689_add_2_7/S1
rtc/sub_3689_add_2_7/S0
rtc/sub_3689_add_2_9/S1
rtc/sub_3689_add_2_9/S0
rtc/sub_3689_add_2_11/S1
rtc/sub_3689_add_2_11/S0
rtc/sub_3689_add_2_13/S1
rtc/sub_3689_add_2_13/S0
rtc/sub_3689_add_2_15/S1
rtc/sub_3689_add_2_15/S0
rtc/sub_3689_add_2_17/S1
rtc/sub_3689_add_2_17/S0
rtc/sub_3689_add_2_19/S1
rtc/sub_3689_add_2_19/S0
rtc/sub_3689_add_2_21/S1
rtc/sub_3689_add_2_21/S0
rtc/sub_3689_add_2_23/S1
rtc/sub_3689_add_2_23/S0
rtc/sub_3689_add_2_25/S1
rtc/sub_3689_add_2_25/S0
rtc/add_18_33/S1
rtc/add_18_33/CO
rtc/sub_3686_add_2_1/S1
rtc/sub_3686_add_2_1/S0
rtc/sub_3686_add_2_1/CI
rtc/sub_3686_add_2_3/S1
rtc/sub_3686_add_2_3/S0
rtc/sub_3686_add_2_5/S1
rtc/sub_3686_add_2_5/S0
rtc/sub_3686_add_2_7/S1
rtc/sub_3686_add_2_7/S0
rtc/sub_3686_add_2_9/S1
rtc/sub_3686_add_2_9/S0
rtc/sub_3686_add_2_11/S1
rtc/sub_3686_add_2_11/S0
rtc/sub_3686_add_2_13/S1
rtc/sub_3686_add_2_13/S0
rtc/sub_3686_add_2_15/S1
rtc/sub_3686_add_2_15/S0
rtc/sub_3686_add_2_17/S1
rtc/sub_3686_add_2_17/S0
rtc/sub_3686_add_2_19/S1
rtc/sub_3686_add_2_19/S0
rtc/sub_3686_add_2_21/S1
rtc/sub_3686_add_2_21/S0
rtc/sub_3686_add_2_23/S1
rtc/sub_3686_add_2_23/S0
rtc/sub_3686_add_2_25/S1
rtc/sub_3686_add_2_25/S0
pgm_addr_12__I_0/alu/t_mult_8u_8u_0_add_2_7/S1
pgm_addr_12__I_0/alu/t_mult_8u_8u_0_add_2_7/COUT
pgm_addr_12__I_0/alu/Cadd_t_mult_8u_8u_0_2_1/S0
......@@ -81,77 +81,77 @@ pgm_addr_12__I_0/alu/mult_8u_8u_0_Cadd_0_4/S1
pgm_addr_12__I_0/alu/mult_8u_8u_0_Cadd_0_4/COUT
pgm_addr_12__I_0/alu/mult_8u_8u_0_cin_lr_add_0/S1
pgm_addr_12__I_0/alu/mult_8u_8u_0_cin_lr_add_0/S0
pgm_addr_12__I_0/alu/add_713_1/S1
pgm_addr_12__I_0/alu/add_713_1/S0
pgm_addr_12__I_0/alu/add_713_1/CI
pgm_addr_12__I_0/alu/add_713_cout/S1
pgm_addr_12__I_0/alu/add_713_cout/CO
pgm_addr_12__I_0/alu/add_710_1/S1
pgm_addr_12__I_0/alu/add_710_1/S0
pgm_addr_12__I_0/alu/add_710_1/CI
pgm_addr_12__I_0/alu/add_710_cout/S1
pgm_addr_12__I_0/alu/add_710_cout/CO
pgm_addr_12__I_0/alu/sub_83_add_2_1/S0
pgm_addr_12__I_0/alu/sub_83_add_2_1/CI
pgm_addr_12__I_0/alu/sub_83_add_2_9/S1
pgm_addr_12__I_0/alu/sub_83_add_2_9/CO
pgm_addr_12__I_0/alu/add_3494_1/S1
pgm_addr_12__I_0/alu/add_3494_1/S0
pgm_addr_12__I_0/alu/add_3494_1/CI
pgm_addr_12__I_0/alu/add_3494_19/S1
pgm_addr_12__I_0/alu/add_3494_19/CO
pgm_addr_12__I_0/wdt_inst/add_35_29/S1
pgm_addr_12__I_0/wdt_inst/add_35_29/CO
pgm_addr_12__I_0/alu/add_3491_1/S1
pgm_addr_12__I_0/alu/add_3491_1/S0
pgm_addr_12__I_0/alu/add_3491_1/CI
pgm_addr_12__I_0/alu/add_3491_19/S1
pgm_addr_12__I_0/alu/add_3491_19/CO
pgm_addr_12__I_0/wdt_inst/add_35_1/S0
pgm_addr_12__I_0/wdt_inst/add_35_1/CI
pgm_addr_12__I_0/wdt_inst/add_35_29/S1
pgm_addr_12__I_0/wdt_inst/add_35_29/CO
pgm_addr_12__I_0/equal_1490_11/S1
pgm_addr_12__I_0/equal_1490_11/S0
pgm_addr_12__I_0/equal_1490_13/S1
pgm_addr_12__I_0/equal_1490_13/S0
pgm_addr_12__I_0/add_1473_15/S1
pgm_addr_12__I_0/add_1473_15/CO
pgm_addr_12__I_0/add_1470_15/S1
pgm_addr_12__I_0/add_1470_15/CO
pgm_addr_12__I_0/equal_1490_15/S1
pgm_addr_12__I_0/equal_1490_15/S0
pgm_addr_12__I_0/equal_1490_16/S0
pgm_addr_12__I_0/equal_1490_16/CO
pgm_addr_12__I_0/add_1816_1/S0
pgm_addr_12__I_0/add_1816_1/CI
pgm_addr_12__I_0/add_4139_1/S0
pgm_addr_12__I_0/add_4139_1/CI
pgm_addr_12__I_0/add_4139_13/S1
pgm_addr_12__I_0/add_4139_13/CO
pgm_addr_12__I_0/add_1816_15/S1
pgm_addr_12__I_0/add_1816_15/CO
pgm_addr_12__I_0/add_5587_1/S0
pgm_addr_12__I_0/add_5587_1/CI
pgm_addr_12__I_0/add_5587_13/CO
pgm_addr_12__I_0/add_4136_1/S0
pgm_addr_12__I_0/add_4136_1/CI
pgm_addr_12__I_0/add_4136_13/S1
pgm_addr_12__I_0/add_4136_13/CO
pgm_addr_12__I_0/add_5583_1/S0
pgm_addr_12__I_0/add_5583_1/CI
pgm_addr_12__I_0/add_5583_13/CO
pgm_addr_12__I_0/sub_13_add_2_1/S0
pgm_addr_12__I_0/sub_13_add_2_1/CI
pgm_addr_12__I_0/add_1474_1/S1
pgm_addr_12__I_0/add_1474_1/S0
pgm_addr_12__I_0/add_1474_1/CI
pgm_addr_12__I_0/equal_1490_0/S1
pgm_addr_12__I_0/equal_1490_0/S0
pgm_addr_12__I_0/equal_1490_0/CI
pgm_addr_12__I_0/equal_1490_16/S0
pgm_addr_12__I_0/equal_1490_16/CO
pgm_addr_12__I_0/sub_13_add_2_15/S1
pgm_addr_12__I_0/sub_13_add_2_15/CO
pgm_addr_12__I_0/sub_12_add_2_1/S0
pgm_addr_12__I_0/sub_12_add_2_1/CI
pgm_addr_12__I_0/sub_12_add_2_15/S1
pgm_addr_12__I_0/sub_12_add_2_15/CO
pgm_addr_12__I_0/add_1474_15/S1
pgm_addr_12__I_0/add_1474_15/CO
pgm_addr_12__I_0/add_1818_1/S1
pgm_addr_12__I_0/add_1818_1/S0
pgm_addr_12__I_0/add_1818_1/CI
pgm_addr_12__I_0/add_1814_1/S0
pgm_addr_12__I_0/add_1814_1/CI
pgm_addr_12__I_0/add_1816_1/S0
pgm_addr_12__I_0/add_1816_1/CI
pgm_addr_12__I_0/add_1814_13/CO
pgm_addr_12__I_0/add_1816_15/S1
pgm_addr_12__I_0/add_1816_15/CO
pgm_addr_12__I_0/add_1471_1/S1
pgm_addr_12__I_0/add_1471_1/S0
pgm_addr_12__I_0/add_1471_1/CI
pgm_addr_12__I_0/add_1471_15/S1
pgm_addr_12__I_0/add_1471_15/CO
pgm_addr_12__I_0/add_1818_1/S1
pgm_addr_12__I_0/add_1818_1/S0
pgm_addr_12__I_0/add_1818_1/CI
pgm_addr_12__I_0/equal_1490_0/S1
pgm_addr_12__I_0/equal_1490_0/S0
pgm_addr_12__I_0/equal_1490_0/CI
pgm_addr_12__I_0/add_1818_15/CO
pgm_addr_12__I_0/add_1473_1/S0
pgm_addr_12__I_0/add_1473_1/CI
pgm_addr_12__I_0/equal_1490_11/S1
pgm_addr_12__I_0/equal_1490_11/S0
pgm_addr_12__I_0/add_1470_1/S0
pgm_addr_12__I_0/add_1470_1/CI