Commit 55e82090 authored by Iulian Gheorghiu's avatar Iulian Gheorghiu

Update README.md

parent bacfd951
......@@ -18,7 +18,7 @@ Utilization report from implementation for CORE_TYPE_XMEGA:
This results are with two configurable paralel ports, 1KByte of RAM and ~ 512 Bytes of ROM.
The IP was moved to https://git.morgothdisk.com/MorgothCreator/VHDL-UTIL-IP directory, here is only the implementation project with implementation top and simulation top.
The IP was moved to https://git.morgothdisk.com/VERILOG/VERILOG-UTIL-IP directory, here is only the implementation project with implementation top and simulation top.
More details about instruction set implementation of different core type you can read here: https://en.wikipedia.org/wiki/Atmel_AVR_instruction_set
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