Commit 31a57805 authored by Iulian Gheorghiu's avatar Iulian Gheorghiu

Update

parent 19f7a1f4
......@@ -30,7 +30,7 @@
<Source name="../VERILOG-UTIL-IP/xmega_core/io/io_s_h.v" type="Verilog" type_short="Verilog">
<Options/>
</Source>
<Source name="../VERILOG-UTIL-IP/memory.v" type="Verilog" type_short="Verilog">
<Source name="../VERILOG-UTIL-IP/helpers/memory.v" type="Verilog" type_short="Verilog">
<Options/>
</Source>
<Source name="core1ROM.mem" type="Unknown Type" type_short="Unknown">
......
......@@ -14,6 +14,32 @@ prj_project open "C:/GitHub/XMEGA-CORE-IP-TST-LATTICE/XmegaCoreIpTstLattice.ldf"
<A name="pn180817222252"></A><B><U><big>pn180817222252</big></U></B>
#Start recording tcl command: 8/17/2018 20:33:59
#Project Location: C:/GitHub/VERILOG-XMEGA-CORE-IP-TST-LATTICE; Project name: XmegaCoreIpTstLattice
prj_project open "C:/GitHub/VERILOG-XMEGA-CORE-IP-TST-LATTICE/XmegaCoreIpTstLattice.ldf"
prj_src remove "C:/GitHub/VHDL-UTIL-IP/memory.v" "C:/GitHub/VHDL-UTIL-IP/xmega_core/mega_core_opt.v" "C:/GitHub/VHDL-UTIL-IP/xmega_core/io/pio_s.v" "C:/GitHub/VHDL-UTIL-IP/xmega_core/io/pio.v" "C:/GitHub/VHDL-UTIL-IP/xmega_core/io/io_uart.v" "C:/GitHub/VHDL-UTIL-IP/xmega_core/io/io_spi.v" "C:/GitHub/VHDL-UTIL-IP/xmega_core/io/io_s_h.v" "C:/GitHub/VHDL-UTIL-IP/xmega_core/io/io_i2c.v" "C:/GitHub/VHDL-UTIL-IP/xmega_core/io/io.v" "C:/GitHub/VHDL-UTIL-IP/xmega_core/sim_uc.v"
prj_src add "C:/GitHub/VERILOG-UTIL-IP/xmega_core/mega_core_opt.v" "C:/GitHub/VERILOG-UTIL-IP/xmega_core/sim_uc.v"
prj_src add "C:/GitHub/VERILOG-UTIL-IP/xmega_core/io/uart_s.v" "C:/GitHub/VERILOG-UTIL-IP/xmega_core/io/twi_s.v" "C:/GitHub/VERILOG-UTIL-IP/xmega_core/io/spi_s.v" "C:/GitHub/VERILOG-UTIL-IP/xmega_core/io/rtc_s.v" "C:/GitHub/VERILOG-UTIL-IP/xmega_core/io/pio_s.v" "C:/GitHub/VERILOG-UTIL-IP/xmega_core/io/io_s_h.v"
prj_run Synthesis -impl impl1
prj_run Synthesis -impl impl1
prj_src add "C:/GitHub/VERILOG-UTIL-IP/memory.v"
prj_run Synthesis -impl impl1
prj_run Synthesis -impl impl1
prj_run Export -impl impl1
rva_project open "C:/GitHub/VERILOG-XMEGA-CORE-IP-TST-LATTICE/untitled.rva"
rva_project close
rva_project open "C:/GitHub/VERILOG-XMEGA-CORE-IP-TST-LATTICE/untitled.rva"
rvl_project open C:/GitHub/VERILOG-XMEGA-CORE-IP-TST-LATTICE/xmega.rvl
prj_src exclude "C:/GitHub/VERILOG-XMEGA-CORE-IP-TST-LATTICE/untitled.rva"
rvl_project close -force
rva_project close
prj_run Export -impl impl1
prj_run Export -impl impl1 -forceAll
#Stop recording: 8/17/2018 22:22:52
<BR>
<BR>
<BR>
......
#Start recording tcl command: 9/11/2018 19:49:37
#Project Location: C:/GitHub/VERILOG-XMEGA-CORE-IP-TST-LATTICE; Project name: XmegaCoreIpTstLattice
prj_project open "C:/GitHub/VERILOG-XMEGA-CORE-IP-TST-LATTICE/XmegaCoreIpTstLattice.ldf"
prj_src remove "C:/GitHub/VERILOG-UTIL-IP/memory.v"
prj_src add "C:/GitHub/VERILOG-UTIL-IP/helpers/memory.v"
#Stop recording: 9/12/2018 01:13:00
This diff is collapsed.
......@@ -3,30 +3,30 @@
<Strategy name="Strategy1">
<Milestone name="Export" build_result="0" build_time="0">
<Task name="IBIS" build_result="0" update_result="2" update_time="1528969056"/>
<Task name="TimingSimFileVlg" build_result="2" update_result="0" update_time="1534530814"/>
<Task name="TimingSimFileVlg" build_result="0" update_result="2" update_time="1534530814"/>
<Task name="TimingSimFileVHD" build_result="0" update_result="3" update_time="0"/>
<Task name="Bitgen" build_result="2" update_result="0" update_time="1534530819"/>
<Task name="Bitgen" build_result="0" update_result="2" update_time="1534530819"/>
<Task name="Jedecgen" build_result="0" update_result="3" update_time="0"/>
<Task name="Jedec4Xo3l" build_result="0" update_result="3" update_time="0"/>
<Task name="Bitgen4Xo3l" build_result="0" update_result="3" update_time="0"/>
</Milestone>
<Milestone name="Map" build_result="2" build_time="1534530494">
<Task name="Map" build_result="2" update_result="0" update_time="1534530494"/>
<Task name="MapTrace" build_result="2" update_result="0" update_time="1534530496"/>
<Task name="MapVerilogSimFile" build_result="2" update_result="0" update_time="1534530504"/>
<Milestone name="Map" build_result="0" build_time="1534530494">
<Task name="Map" build_result="0" update_result="2" update_time="1534530494"/>
<Task name="MapTrace" build_result="0" update_result="2" update_time="1534530496"/>
<Task name="MapVerilogSimFile" build_result="0" update_result="2" update_time="1534530504"/>
<Task name="MapVHDLSimFile" build_result="0" update_result="3" update_time="0"/>
</Milestone>
<Milestone name="PAR" build_result="2" build_time="1534530793">
<Task name="PAR" build_result="2" update_result="0" update_time="1534530793"/>
<Task name="PARTrace" build_result="2" update_result="0" update_time="1534530796"/>
<Task name="IOTiming" build_result="2" update_result="0" update_time="1534530803"/>
<Milestone name="PAR" build_result="0" build_time="1534530793">
<Task name="PAR" build_result="0" update_result="2" update_time="1534530793"/>
<Task name="PARTrace" build_result="0" update_result="2" update_time="1534530796"/>
<Task name="IOTiming" build_result="0" update_result="2" update_time="1534530803"/>
</Milestone>
<Milestone name="Synthesis" build_result="2" build_time="1534530487">
<Task name="Lattice_Synthesis" build_result="2" update_result="0" update_time="1534530487"/>
<Task name="LSE_Compile" build_result="2" update_result="0" update_time="1534530241"/>
<Milestone name="Synthesis" build_result="0" build_time="1534530487">
<Task name="Lattice_Synthesis" build_result="0" update_result="2" update_time="1534530487"/>
<Task name="LSE_Compile" build_result="0" update_result="2" update_time="1534530241"/>
</Milestone>
<Milestone name="TOOL_Report" build_result="0" build_time="0">
<Task name="HDLE" build_result="0" update_result="2" update_time="1534529007"/>
<Task name="HDLE" build_result="2" update_result="0" update_time="1536685059"/>
<Task name="DEC" build_result="0" update_result="2" update_time="0"/>
<Task name="SSO" build_result="0" update_result="2" update_time="1528979648"/>
<Task name="PIODRC" build_result="0" update_result="2" update_time="0"/>
......
......@@ -24,9 +24,9 @@
</TR>
<TR>
<TD align='left' BGCOLOR='#DEE8F4' COLSPAN='1'><SPAN style="COLOR: #000000">Last Process:</SPAN></TD>
<TD align='left' BGCOLOR='#FFFFFF' COLSPAN='1'><SPAN style="COLOR: #000000">Bitstream File</SPAN></TD>
<TD align='left' BGCOLOR='#FFFFFF' COLSPAN='1'><SPAN style="COLOR: #000000"></SPAN></TD>
<TD align='left' BGCOLOR='#DEE8F4' COLSPAN='1'><SPAN style="COLOR: #000000">State:</SPAN></TD>
<TD align='left' BGCOLOR='#FFFFFF' COLSPAN='1'><SPAN style="COLOR: #000000">Passed</SPAN></TD>
<TD align='left' BGCOLOR='#FFFFFF' COLSPAN='1'><SPAN style="COLOR: #000000"></SPAN></TD>
</TR>
<TR>
<TD align='left' BGCOLOR='#DEE8F4' COLSPAN='1'><SPAN style="COLOR: #000000">Target Device:</SPAN></TD>
......@@ -62,7 +62,7 @@
</TR>
<TR>
<TD align='left' BGCOLOR='#DEE8F4' COLSPAN='1'><SPAN style="COLOR: #000000">Updated:</SPAN></TD>
<TD align='left' BGCOLOR='#FFFFFF' COLSPAN='3'><SPAN style="COLOR: #000000">2018/08/17 21:46:41</SPAN></TD>
<TD align='left' BGCOLOR='#FFFFFF' COLSPAN='3'><SPAN style="COLOR: #000000">2018/09/11 21:07:19</SPAN></TD>
</TR>
<TR>
<TD align='left' BGCOLOR='#DEE8F4' COLSPAN='1'><SPAN style="COLOR: #000000">Implementation Location:</SPAN></TD>
......
......@@ -4,6 +4,11 @@ Starting: parse design source files
(VERI-1482) Analyzing Verilog file C:/GitHub/VERILOG-XMEGA-CORE-IP-TST-LATTICE/top_uc.v
(VERI-1482) Analyzing Verilog file C:/GitHub/VERILOG-UTIL-IP/xmega_core/mega_core_opt.v
(VERI-1482) Analyzing Verilog file C:/GitHub/VERILOG-UTIL-IP/xmega_core/sim_uc.v
ERROR - C:/GitHub/VERILOG-UTIL-IP/xmega_core/sim_uc.v(22,10-22,20) (VERI-1245) cannot open include file ddr3_v.v
ERROR - C:/GitHub/VERILOG-UTIL-IP/xmega_core/sim_uc.v(40,1-40,10) (VERI-1158) use of undefined macro DDR3_TOP
ERROR - C:/GitHub/VERILOG-UTIL-IP/xmega_core/sim_uc.v(43,1-43,9) (VERI-1158) use of undefined macro DDR3_IO
ERROR - C:/GitHub/VERILOG-UTIL-IP/xmega_core/sim_uc.v(39,1-400,10) (VERI-1072) module sim_uc ignored due to previous errors
(VERI-1483) Verilog file C:/GitHub/VERILOG-UTIL-IP/xmega_core/sim_uc.v ignored due to errors
(VERI-1482) Analyzing Verilog file C:/GitHub/VERILOG-UTIL-IP/xmega_core/io/uart_s.v
INFO - C:/GitHub/VERILOG-UTIL-IP/xmega_core/io/uart_s.v(23,10-23,20) (VERI-1328) analyzing included file C:/GitHub/VERILOG-UTIL-IP/xmega_core/io/io_s_h.v
(VERI-1482) Analyzing Verilog file C:/GitHub/VERILOG-UTIL-IP/xmega_core/io/twi_s.v
......@@ -13,48 +18,31 @@ INFO - C:/GitHub/VERILOG-UTIL-IP/xmega_core/io/spi_s.v(23,10-23,20) (VERI-1328)
(VERI-1482) Analyzing Verilog file C:/GitHub/VERILOG-UTIL-IP/xmega_core/io/rtc_s.v
INFO - C:/GitHub/VERILOG-UTIL-IP/xmega_core/io/rtc_s.v(22,10-22,20) (VERI-1328) analyzing included file C:/GitHub/VERILOG-UTIL-IP/xmega_core/io/io_s_h.v
(VERI-1482) Analyzing Verilog file C:/GitHub/VERILOG-UTIL-IP/xmega_core/io/pio_s.v
INFO - C:/GitHub/VERILOG-UTIL-IP/xmega_core/io/pio_s.v(23,10-23,20) (VERI-1328) analyzing included file C:/GitHub/VERILOG-UTIL-IP/xmega_core/io/io_s_h.v
INFO - C:/GitHub/VERILOG-UTIL-IP/xmega_core/io/pio_s.v(22,10-22,20) (VERI-1328) analyzing included file C:/GitHub/VERILOG-UTIL-IP/xmega_core/io/io_s_h.v
(VERI-1482) Analyzing Verilog file C:/GitHub/VERILOG-UTIL-IP/xmega_core/io/io_s_h.v
(VERI-1482) Analyzing Verilog file C:/GitHub/VERILOG-UTIL-IP/memory.v
(VERI-1482) Analyzing Verilog file C:/GitHub/VERILOG-UTIL-IP/helpers/memory.v
INFO - C:/GitHub/VERILOG-XMEGA-CORE-IP-TST-LATTICE/top_uc.v(35,8-35,14) (VERI-1018) compiling module top_uc
INFO - C:/GitHub/VERILOG-XMEGA-CORE-IP-TST-LATTICE/top_uc.v(35,1-278,10) (VERI-9000) elaborating module 'top_uc'
INFO - C:/GitHub/VERILOG-XMEGA-CORE-IP-TST-LATTICE/top_uc.v(35,1-281,10) (VERI-9000) elaborating module 'top_uc'
INFO - C:/lscc/diamond/3.10_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo3l.v(1759,1-1764,10) (VERI-9000) elaborating module 'OSCH_uniq_1'
INFO - C:/GitHub/VERILOG-UTIL-IP/xmega_core/io/rtc_s.v(24,1-300,10) (VERI-9000) elaborating module 'rtc_s_uniq_1'
INFO - C:/GitHub/VERILOG-UTIL-IP/xmega_core/io/pio_s.v(25,1-243,10) (VERI-9000) elaborating module 'pio_s_uniq_1'
INFO - C:/GitHub/VERILOG-UTIL-IP/xmega_core/io/pio_s.v(25,1-243,10) (VERI-9000) elaborating module 'pio_s_uniq_2'
INFO - C:/GitHub/VERILOG-UTIL-IP/xmega_core/io/pio_s.v(25,1-243,10) (VERI-9000) elaborating module 'pio_s_uniq_3'
INFO - C:/GitHub/VERILOG-UTIL-IP/xmega_core/io/uart_s.v(25,1-464,10) (VERI-9000) elaborating module 'uart_s_uniq_1'
INFO - C:/GitHub/VERILOG-UTIL-IP/memory.v(23,1-66,10) (VERI-9000) elaborating module 'rom_uniq_1'
INFO - C:/GitHub/VERILOG-UTIL-IP/memory.v(69,1-113,10) (VERI-9000) elaborating module 'ram_uniq_1'
INFO - C:/GitHub/VERILOG-UTIL-IP/xmega_core/mega_core_opt.v(991,1-2963,10) (VERI-9000) elaborating module 'mega_core_uniq_1'
INFO - C:/GitHub/VERILOG-UTIL-IP/xmega_core/mega_core_opt.v(913,1-978,10) (VERI-9000) elaborating module 'int_encoder_uniq_1'
INFO - C:/GitHub/VERILOG-UTIL-IP/xmega_core/io/pio_s.v(24,1-242,10) (VERI-9000) elaborating module 'pio_s_uniq_1'
INFO - C:/GitHub/VERILOG-UTIL-IP/xmega_core/io/pio_s.v(24,1-242,10) (VERI-9000) elaborating module 'pio_s_uniq_2'
INFO - C:/GitHub/VERILOG-UTIL-IP/xmega_core/io/pio_s.v(24,1-242,10) (VERI-9000) elaborating module 'pio_s_uniq_3'
INFO - C:/GitHub/VERILOG-UTIL-IP/xmega_core/io/uart_s.v(25,1-476,10) (VERI-9000) elaborating module 'uart_s_uniq_1'
INFO - C:/GitHub/VERILOG-UTIL-IP/helpers/memory.v(23,1-66,10) (VERI-9000) elaborating module 'rom_uniq_1'
INFO - C:/GitHub/VERILOG-UTIL-IP/helpers/memory.v(69,1-113,10) (VERI-9000) elaborating module 'ram_uniq_1'
INFO - C:/GitHub/VERILOG-UTIL-IP/xmega_core/mega_core_opt.v(992,1-2999,10) (VERI-9000) elaborating module 'mega_core_uniq_1'
INFO - C:/GitHub/VERILOG-UTIL-IP/xmega_core/mega_core_opt.v(914,1-979,10) (VERI-9000) elaborating module 'int_encoder_uniq_1'
INFO - C:/GitHub/VERILOG-UTIL-IP/xmega_core/mega_core_opt.v(204,1-426,10) (VERI-9000) elaborating module 'inst_dec_uniq_1'
INFO - C:/GitHub/VERILOG-UTIL-IP/xmega_core/mega_core_opt.v(443,1-493,10) (VERI-9000) elaborating module 'mega_regs_uniq_1'
INFO - C:/GitHub/VERILOG-UTIL-IP/xmega_core/mega_core_opt.v(501,1-905,10) (VERI-9000) elaborating module 'mega_alu_uniq_1'
INFO - C:/GitHub/VERILOG-UTIL-IP/xmega_core/mega_core_opt.v(501,1-906,10) (VERI-9000) elaborating module 'mega_alu_uniq_1'
INFO - C:/GitHub/VERILOG-UTIL-IP/xmega_core/mega_core_opt.v(47,1-109,10) (VERI-9000) elaborating module 'watchdog_uniq_1'
WARNING - C:/GitHub/VERILOG-XMEGA-CORE-IP-TST-LATTICE/top_uc.v(202,1-221,4) (VERI-1927) port int_rst remains unconnected for this instance
WARNING - C:/GitHub/VERILOG-XMEGA-CORE-IP-TST-LATTICE/top_uc.v(247,1-276,3) (VERI-1927) port int_rst remains unconnected for this instance
WARNING - C:/GitHub/VERILOG-XMEGA-CORE-IP-TST-LATTICE/top_uc.v(147,2-147,10) (VERI-1330) actual bit length 4 differs from formal bit length 8 for port io
INFO - C:/GitHub/VERILOG-UTIL-IP/xmega_core/sim_uc.v(35,8-35,14) (VERI-1018) compiling module sim_uc
INFO - C:/GitHub/VERILOG-UTIL-IP/xmega_core/sim_uc.v(35,1-284,10) (VERI-9000) elaborating module 'sim_uc'
INFO - C:/GitHub/VERILOG-UTIL-IP/xmega_core/io/rtc_s.v(24,1-300,10) (VERI-9000) elaborating module 'rtc_s_uniq_2'
INFO - C:/GitHub/VERILOG-UTIL-IP/xmega_core/io/pio_s.v(25,1-243,10) (VERI-9000) elaborating module 'pio_s_uniq_4'
INFO - C:/GitHub/VERILOG-UTIL-IP/xmega_core/io/pio_s.v(25,1-243,10) (VERI-9000) elaborating module 'pio_s_uniq_5'
INFO - C:/GitHub/VERILOG-UTIL-IP/xmega_core/io/pio_s.v(25,1-243,10) (VERI-9000) elaborating module 'pio_s_uniq_6'
INFO - C:/GitHub/VERILOG-UTIL-IP/xmega_core/io/uart_s.v(25,1-464,10) (VERI-9000) elaborating module 'uart_s_uniq_2'
INFO - C:/GitHub/VERILOG-UTIL-IP/memory.v(23,1-66,10) (VERI-9000) elaborating module 'rom_uniq_2'
INFO - C:/GitHub/VERILOG-UTIL-IP/memory.v(69,1-113,10) (VERI-9000) elaborating module 'ram_uniq_2'
INFO - C:/GitHub/VERILOG-UTIL-IP/xmega_core/mega_core_opt.v(991,1-2963,10) (VERI-9000) elaborating module 'mega_core_uniq_2'
INFO - C:/GitHub/VERILOG-UTIL-IP/xmega_core/mega_core_opt.v(913,1-978,10) (VERI-9000) elaborating module 'int_encoder_uniq_2'
INFO - C:/GitHub/VERILOG-UTIL-IP/xmega_core/mega_core_opt.v(204,1-426,10) (VERI-9000) elaborating module 'inst_dec_uniq_2'
INFO - C:/GitHub/VERILOG-UTIL-IP/xmega_core/mega_core_opt.v(443,1-493,10) (VERI-9000) elaborating module 'mega_regs_uniq_2'
INFO - C:/GitHub/VERILOG-UTIL-IP/xmega_core/mega_core_opt.v(501,1-905,10) (VERI-9000) elaborating module 'mega_alu_uniq_2'
INFO - C:/GitHub/VERILOG-UTIL-IP/xmega_core/mega_core_opt.v(47,1-109,10) (VERI-9000) elaborating module 'watchdog_uniq_2'
WARNING - C:/GitHub/VERILOG-UTIL-IP/xmega_core/sim_uc.v(185,1-204,4) (VERI-1927) port int_rst remains unconnected for this instance
INFO - C:/GitHub/VERILOG-UTIL-IP/xmega_core/io/twi_s.v(25,8-25,13) (VERI-1018) compiling module twi_s
INFO - C:/GitHub/VERILOG-UTIL-IP/xmega_core/io/twi_s.v(25,1-74,10) (VERI-9000) elaborating module 'twi_s'
INFO - C:/GitHub/VERILOG-UTIL-IP/xmega_core/io/spi_s.v(25,8-25,13) (VERI-1018) compiling module spi_s
INFO - C:/GitHub/VERILOG-UTIL-IP/xmega_core/io/spi_s.v(25,1-72,10) (VERI-9000) elaborating module 'spi_s'
Done: design load finished with (0) errors, and (4) warnings
Done: design load finished with (4) errors, and (2) warnings
</PRE></BODY></HTML>
\ No newline at end of file
<?xml version="1.0" encoding="UTF-8"?>
<userSetting name="C:/GitHub/VERILOG-XMEGA-CORE-IP-TST-LATTICE/promote.xml" version="Diamond (64-bit) 3.10.2.115" date="Fri Aug 17 22:22:52 2018" vendor="Lattice Semiconductor Corporation" >
<userSetting name="C:/GitHub/VERILOG-XMEGA-CORE-IP-TST-LATTICE/promote.xml" version="Diamond (64-bit) 3.10.2.115" date="Wed Sep 12 01:13:00 2018" vendor="Lattice Semiconductor Corporation" >
<msg mid="35931002" type="Warning" />
<msg mid="35901402" type="Warning" />
<msg mid="35901012" type="Error" />
......
......@@ -60,7 +60,7 @@ wire ram_clk;
3.69 7.39 14.78 88.67
3.91 7.82 15.65 133.00
*/
OSCH #(.NOM_FREQ(2.08)) rc_osc(.STDBY(1'b0), .SEDSTDBY(), .OSC(ram_clk));
OSCH #(.NOM_FREQ(15.65)) rc_osc(.STDBY(1'b0), .SEDSTDBY(), .OSC(ram_clk));
reg [7:0]led_tmp;
assign leds = led_tmp;
......@@ -201,8 +201,8 @@ pio_s # (
uart_s # (
.BAUDRATE_COUNTER_LENGTH(12),
.DINAMIC_BAUDRATE("TRUE"),
.BAUDRATE_DIVIDER((1000 / 24) / 16 / 19200),
.DINAMIC_BAUDRATE("FALSE"),
.BAUDRATE_DIVIDER(15650000 / 16 / 115200),
.ADDRESS('hC0),
.BUS_ADDR_DATA_LEN(`BUS_ADDR_DATA_LEN)
) uart_A (
......
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