Commit 19f7a1f4 authored by Iulian Gheorghiu's avatar Iulian Gheorghiu

Multiple updates

parent 55e82090
......@@ -11,4 +11,4 @@ showUGROUPs=true
showPARITIONs=true
showLogicalConnections=false
dontShowBBoxOverlapWarning=false
sceneInViewRect=@Variant(\0\0\0\x14\xc0\xeaJ\xb0`&u\xca\xc0\xa2\x85\x1d>\xe5\xf5\x96\x41\x10\xed\xac\xbb~2{@\xfa\xa9\xef?\xb3\x14p)
sceneInViewRect=@Variant(\0\0\0\x14\xc1\0\xa3\x8b\x84\0\0\0\xc0\xa7T\xb2\0\0\0\0\x41\x1b\0\x98L\0\0\0@\xfa\xf9\xed\xd0\0\0\0)
......@@ -21,5 +21,5 @@ Name=100
SortColumns="2,"
[MemoryTreeView]
EBR%20Configuration=314
Setting=1250
EBR%20Configuration=1022
Setting=1027
......@@ -2,38 +2,35 @@
<BaliProject version="3.2" title="XmegaCoreIpTstLattice" device="LCMXO3LF-6900C-5BG256C" default_implementation="impl1">
<Options/>
<Implementation title="impl1" dir="impl1" description="impl1" synthesis="lse" default_strategy="Strategy1">
<Options def_top="top_uc" top="top_uc"/>
<Source name="../VHDL-UTIL-IP/xmega_core/sim_uc.v" type="Verilog" type_short="Verilog">
<Options/>
<Options def_top="spi_s" top="top_uc"/>
<Source name="top_uc.v" type="Verilog" type_short="Verilog">
<Options top_module="top_uc"/>
</Source>
<Source name="../VHDL-UTIL-IP/xmega_core/io/io.v" type="Verilog" type_short="Verilog">
<Source name="../VERILOG-UTIL-IP/xmega_core/mega_core_opt.v" type="Verilog" type_short="Verilog">
<Options/>
</Source>
<Source name="../VHDL-UTIL-IP/xmega_core/io/io_i2c.v" type="Verilog" type_short="Verilog">
<Source name="../VERILOG-UTIL-IP/xmega_core/sim_uc.v" type="Verilog" type_short="Verilog">
<Options/>
</Source>
<Source name="../VHDL-UTIL-IP/xmega_core/io/io_s_h.v" type="Verilog" type_short="Verilog">
<Source name="../VERILOG-UTIL-IP/xmega_core/io/uart_s.v" type="Verilog" type_short="Verilog">
<Options/>
</Source>
<Source name="../VHDL-UTIL-IP/xmega_core/io/io_spi.v" type="Verilog" type_short="Verilog">
<Source name="../VERILOG-UTIL-IP/xmega_core/io/twi_s.v" type="Verilog" type_short="Verilog">
<Options/>
</Source>
<Source name="../VHDL-UTIL-IP/xmega_core/io/io_uart.v" type="Verilog" type_short="Verilog">
<Source name="../VERILOG-UTIL-IP/xmega_core/io/spi_s.v" type="Verilog" type_short="Verilog">
<Options/>
</Source>
<Source name="../VHDL-UTIL-IP/xmega_core/io/pio.v" type="Verilog" type_short="Verilog">
<Source name="../VERILOG-UTIL-IP/xmega_core/io/rtc_s.v" type="Verilog" type_short="Verilog">
<Options/>
</Source>
<Source name="../VHDL-UTIL-IP/xmega_core/io/pio_s.v" type="Verilog" type_short="Verilog">
<Source name="../VERILOG-UTIL-IP/xmega_core/io/pio_s.v" type="Verilog" type_short="Verilog">
<Options/>
</Source>
<Source name="top_uc.v" type="Verilog" type_short="Verilog">
<Options top_module="top_uc"/>
</Source>
<Source name="../VHDL-UTIL-IP/xmega_core/mega_core_opt.v" type="Verilog" type_short="Verilog">
<Source name="../VERILOG-UTIL-IP/xmega_core/io/io_s_h.v" type="Verilog" type_short="Verilog">
<Options/>
</Source>
<Source name="../VHDL-UTIL-IP/memory.v" type="Verilog" type_short="Verilog">
<Source name="../VERILOG-UTIL-IP/memory.v" type="Verilog" type_short="Verilog">
<Options/>
</Source>
<Source name="core1ROM.mem" type="Unknown Type" type_short="Unknown">
......@@ -45,7 +42,7 @@
<Source name="sim/sim.spf" type="Simulation Project File" type_short="SPF">
<Options/>
</Source>
<Source name="untitled.rva" type="Reveal Analyzer Project File" type_short="RVA">
<Source name="untitled.rva" type="Reveal Analyzer Project File" type_short="RVA" excluded="TRUE">
<Options/>
</Source>
<Source name="xmega.rvl" type="Reveal" type_short="Reveal">
......
#Start recording tcl command: 8/17/2018 20:33:59
#Project Location: C:/GitHub/VERILOG-XMEGA-CORE-IP-TST-LATTICE; Project name: XmegaCoreIpTstLattice
prj_project open "C:/GitHub/VERILOG-XMEGA-CORE-IP-TST-LATTICE/XmegaCoreIpTstLattice.ldf"
prj_src remove "C:/GitHub/VHDL-UTIL-IP/memory.v" "C:/GitHub/VHDL-UTIL-IP/xmega_core/mega_core_opt.v" "C:/GitHub/VHDL-UTIL-IP/xmega_core/io/pio_s.v" "C:/GitHub/VHDL-UTIL-IP/xmega_core/io/pio.v" "C:/GitHub/VHDL-UTIL-IP/xmega_core/io/io_uart.v" "C:/GitHub/VHDL-UTIL-IP/xmega_core/io/io_spi.v" "C:/GitHub/VHDL-UTIL-IP/xmega_core/io/io_s_h.v" "C:/GitHub/VHDL-UTIL-IP/xmega_core/io/io_i2c.v" "C:/GitHub/VHDL-UTIL-IP/xmega_core/io/io.v" "C:/GitHub/VHDL-UTIL-IP/xmega_core/sim_uc.v"
prj_src add "C:/GitHub/VERILOG-UTIL-IP/xmega_core/mega_core_opt.v" "C:/GitHub/VERILOG-UTIL-IP/xmega_core/sim_uc.v"
prj_src add "C:/GitHub/VERILOG-UTIL-IP/xmega_core/io/uart_s.v" "C:/GitHub/VERILOG-UTIL-IP/xmega_core/io/twi_s.v" "C:/GitHub/VERILOG-UTIL-IP/xmega_core/io/spi_s.v" "C:/GitHub/VERILOG-UTIL-IP/xmega_core/io/rtc_s.v" "C:/GitHub/VERILOG-UTIL-IP/xmega_core/io/pio_s.v" "C:/GitHub/VERILOG-UTIL-IP/xmega_core/io/io_s_h.v"
prj_run Synthesis -impl impl1
prj_run Synthesis -impl impl1
prj_src add "C:/GitHub/VERILOG-UTIL-IP/memory.v"
prj_run Synthesis -impl impl1
prj_run Synthesis -impl impl1
prj_run Export -impl impl1
rva_project open "C:/GitHub/VERILOG-XMEGA-CORE-IP-TST-LATTICE/untitled.rva"
rva_project close
rva_project open "C:/GitHub/VERILOG-XMEGA-CORE-IP-TST-LATTICE/untitled.rva"
rvl_project open C:/GitHub/VERILOG-XMEGA-CORE-IP-TST-LATTICE/xmega.rvl
prj_src exclude "C:/GitHub/VERILOG-XMEGA-CORE-IP-TST-LATTICE/untitled.rva"
rvl_project close -force
rva_project close
prj_run Export -impl impl1
prj_run Export -impl impl1 -forceAll
#Stop recording: 8/17/2018 22:22:52
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......@@ -76,72 +84,166 @@ C013
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......@@ -153,219 +255,161 @@ B7DE
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......@@ -382,219 +426,161 @@ B7DE
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