...
 
Commits (6)
......@@ -81,7 +81,7 @@ module ram #(
);
(* ram_style="block" *)
reg [DATA_BUS_WIDTH - 1:0] mem [(2**ADDR_BUS_WIDTH-1):0];
reg [DATA_BUS_WIDTH - 1:0] mem [(2**ADDR_BUS_WIDTH)-1:0];
initial begin
if (RAM_PATH != "")
......
......@@ -21,13 +21,6 @@
`include "io_s_h.v"
`define GFX_ACCEL_IDLE 0
`define GFX_ACCEL_VRAM_ACCESS 1
`define GFX_ACCEL_PIXEL_LOAD 2
`define GFX_ACCEL_PIXEL 3
`define GFX_ACCEL_CTRL_ACCESS 4
`define GFX_ACCEL_FILL_RECT 5
/*
* The first sixteen addresses after ADDRESS parameter address are used by LCD IP, the next sixteen addresses are used by this IP.
*/
......@@ -189,19 +182,19 @@ begin
if(wr_int && !CMD)
begin
case(ctrl_addr[4:0])
'd16: CMD <= ctrl_data_in;
'd18: CLIP_X_MIN <= {tmp_write, ctrl_data_in};
'd19: tmp_write <= ctrl_data_in;
'd20: CLIP_X_MAX <= {tmp_write, ctrl_data_in};
'd21: tmp_write <= ctrl_data_in;
'd22: CLIP_Y_MIN <= {tmp_write, ctrl_data_in};
'd23: tmp_write <= ctrl_data_in;
'd24: CLIP_Y_MAX <= {tmp_write, ctrl_data_in};
'd25: tmp_write <= ctrl_data_in;
'd26: COLOR <= {color_byte_3, color_byte_2, tmp_write, ctrl_data_in};
'd27: tmp_write <= ctrl_data_in;
'd28: color_byte_2 <= ctrl_data_in;
'd29: color_byte_3 <= ctrl_data_in;
`GFX_ACCEL_CMD: CMD <= ctrl_data_in;
`GFX_ACCEL_CLIP_X_MIN_L: CLIP_X_MIN <= {tmp_write, ctrl_data_in};
`GFX_ACCEL_CLIP_X_MIN_H: tmp_write <= ctrl_data_in;
`GFX_ACCEL_CLIP_X_MAX_L: CLIP_X_MAX <= {tmp_write, ctrl_data_in};
`GFX_ACCEL_CLIP_X_MAX_H: tmp_write <= ctrl_data_in;
`GFX_ACCEL_CLIP_Y_MIN_L: CLIP_Y_MIN <= {tmp_write, ctrl_data_in};
`GFX_ACCEL_CLIP_Y_MIN_H: tmp_write <= ctrl_data_in;
`GFX_ACCEL_CLIP_Y_MAX_L: CLIP_Y_MAX <= {tmp_write, ctrl_data_in};
`GFX_ACCEL_CLIP_Y_MAX_H: tmp_write <= ctrl_data_in;
`GFX_ACCEL_BYTE_0: COLOR <= {color_byte_3, color_byte_2, tmp_write, ctrl_data_in};
`GFX_ACCEL_BYTE_1: tmp_write <= ctrl_data_in;
`GFX_ACCEL_BYTE_2: color_byte_2 <= ctrl_data_in;
`GFX_ACCEL_BYTE_3: color_byte_3 <= ctrl_data_in;
endcase
end
else if(!cmd_int && CMD)
......@@ -220,17 +213,17 @@ begin
else
begin
case(cmd_int)
`GFX_ACCEL_VRAM_ACCESS:
`GFX_ACCEL_CMD_VRAM_ACCESS:
begin
direct_vram_access <= 1'b1;
cmd_int <= 'h0;
end
`GFX_ACCEL_CTRL_ACCESS:
`GFX_ACCEL_CMD_CTRL_ACCESS:
begin
direct_vram_access <= 1'b0;
cmd_int <= 'h0;
end
`GFX_ACCEL_PIXEL_LOAD:
`GFX_ACCEL_CMD_PIXEL_LOAD:
begin
x_xnt_int <= CLIP_X_MIN;
y_xnt_int <= CLIP_Y_MIN;
......@@ -242,7 +235,7 @@ begin
end
cmd_int <= 'h0;
end
`GFX_ACCEL_PIXEL:
`GFX_ACCEL_CMD_PIXEL:
begin
color <= COLOR;
if(x_xnt_int >= clip_x_max_int)
......@@ -252,7 +245,7 @@ begin
end
cmd_int <= 'h0;
end
`GFX_ACCEL_FILL_RECT:
`GFX_ACCEL_CMD_FILL_RECT:
begin
if(~new_cmd)
begin
......@@ -284,7 +277,7 @@ begin
if(rd_int)
begin
case(ctrl_addr[4:0])
'd16: ctrl_data_out <= CMD;
`GFX_ACCEL_CMD: ctrl_data_out <= CMD;
default: ctrl_data_out <= 'hz;
endcase
end
......@@ -296,7 +289,7 @@ end
assign lcd_vmem_addr = direct_vram_access ? vmem_addr : (x_xnt_int * H_RES_CONF) + y_xnt_int;
assign lcd_vmem_in = direct_vram_access ? vmem_in : color;
assign vmem_out = direct_vram_access ? vmem_out : 'hz;
assign vmem_out = direct_vram_access ? lcd_vmem_out : 'hz;
assign lcd_vmem_rd = direct_vram_access ? vmem_rd : 1'h0;
assign lcd_vmem_wr = direct_vram_access ? vmem_wr : |cmd_int;
......
......@@ -644,19 +644,47 @@ LCD - LCD display Interface
--------------------------------------------------------------------------
*/
`define LCD_CTRL 0
`define LCD_H_RES_LOW 1
`define LCD_H_RES_HIGH 2
`define LCD_H_PULSE_WIDTH 3
`define LCD_H_BACK_PORCH 4
`define LCD_H_FRONT_PORCH 5
`define LCD_V_RES_LOW 6
`define LCD_V_RES_HIGH 7
`define LCD_V_PULSE_WIDTH 8
`define LCD_V_BACK_PORCH 9
`define LCD_V_FRONT_PORCH 10
`define LCD_PIXEL_SIZE 11
`define LCD_BASE_ADDR_BYTE0 12
`define LCD_BASE_ADDR_BYTE1 13
`define LCD_BASE_ADDR_BYTE2 14
`define LCD_BASE_ADDR_BYTE3 15
`define LCD_CTRL 0
`define LCD_H_RES_LOW 1
`define LCD_H_RES_HIGH 2
`define LCD_H_PULSE_WIDTH 3
`define LCD_H_BACK_PORCH 4
`define LCD_H_FRONT_PORCH 5
`define LCD_V_RES_LOW 6
`define LCD_V_RES_HIGH 7
`define LCD_V_PULSE_WIDTH 8
`define LCD_V_BACK_PORCH 9
`define LCD_V_FRONT_PORCH 10
`define LCD_PIXEL_SIZE 11
`define LCD_BASE_ADDR_BYTE0 12
`define LCD_BASE_ADDR_BYTE1 13
`define LCD_BASE_ADDR_BYTE2 14
`define LCD_BASE_ADDR_BYTE3 15
/*
--------------------------------------------------------------------------
GFX_ACCEL - GFX_ACCEL LCD display 2D accelerator interface
--------------------------------------------------------------------------
*/
`define GFX_ACCEL_CMD 16
`define GFX_ACCEL_CLIP_X_MIN_L 18
`define GFX_ACCEL_CLIP_X_MIN_H 19
`define GFX_ACCEL_CLIP_X_MAX_L 20
`define GFX_ACCEL_CLIP_X_MAX_H 21
`define GFX_ACCEL_CLIP_Y_MIN_L 22
`define GFX_ACCEL_CLIP_Y_MIN_H 23
`define GFX_ACCEL_CLIP_Y_MAX_L 24
`define GFX_ACCEL_CLIP_Y_MAX_H 25
`define GFX_ACCEL_BYTE_0 26
`define GFX_ACCEL_BYTE_1 27
`define GFX_ACCEL_BYTE_2 28
`define GFX_ACCEL_BYTE_3 29
`define GFX_ACCEL_CMD_IDLE 0
`define GFX_ACCEL_CMD_VRAM_ACCESS 1
`define GFX_ACCEL_CMD_PIXEL_LOAD 2
`define GFX_ACCEL_CMD_PIXEL 3
`define GFX_ACCEL_CMD_CTRL_ACCESS 4
`define GFX_ACCEL_CMD_FILL_RECT 5
......@@ -24,7 +24,7 @@
module spi_s #(
parameter DINAMIC_BAUDRATE = "TRUE",
parameter BAUDRATE_DIVIDER = 19200,
parameter BAUDRATE_DIVIDER = 3,
parameter ADDRESS = 0,
parameter BUS_ADDR_DATA_LEN = 16
)(
......@@ -36,11 +36,15 @@ module spi_s #(
input [7:0]bus_in,
output reg[7:0]bus_out,
output int,
inout int_rst
output sck,/* SPI 'sck' signal (output) */
output mosi,/* SPI 'mosi' signal (output) */
input miso,/* SPI 'miso' signal (input) */
output reg ss/* SPI 'ss' signal (if send buffer is maintained full the ss signal will not go high between between transmit chars)(output) */
);
reg [7:0]CTRL;
reg [7:0]BAUD;
//reg [7:0]CTRL;
//reg [7:0]BAUD;
wire cs_int = addr >= ADDRESS && addr < (ADDRESS + 8);
wire rd_int = cs_int && rd;
......@@ -48,25 +52,241 @@ wire wr_int = cs_int && wr;
reg [7:0]baud_cnt;
wire buffempty;
reg [7:0]CTRL;
reg [7:0]INTCTRL;
reg [7:0]STATUS;
localparam WORD_LEN = 8;
localparam PRESCALLER_SIZE = 8;
reg _mosi;
reg charreceivedp;
reg charreceivedn;
reg inbufffullp = 1'b0;
reg inbufffulln = 1'b0;
reg [WORD_LEN - 1:0]input_buffer;
reg [WORD_LEN - 1:0]output_buffer;
assign buffempty = ~(inbufffullp ^ inbufffulln);
reg [2:0]prescallerbuff;
always @ (posedge clk or posedge rst)
begin
if(rst)
begin
inbufffullp <= 1'b0;
prescallerbuff <= 3'b000;
CTRL <= 0;
INTCTRL <= 0;
input_buffer <= 0;
end
else
begin
if(wr_int)
begin
case(addr[2:0])
`SPI_CTRL: CTRL <= bus_in;
`SPI_INTCTRL: INTCTRL <= bus_in;
`SPI_DATA:
begin
if(inbufffullp == inbufffulln && buffempty && CTRL[`SPI_ENABLE_bp])
begin
inbufffullp <= ~inbufffullp;
prescallerbuff <= {CTRL[`SPI_CLK2X_bp], CTRL[`SPI_PRESCALER_gp + 1:`SPI_PRESCALER_gp]};
input_buffer <= bus_in;
end
end
endcase
end
end
end
always @ (posedge clk or posedge rst)
begin
if(rst)
begin
STATUS <= 8'h00;
charreceivedn <= 1'b0;
end
else if(rd_int)
begin
case(addr[2:0])
`SPI_DATA: STATUS[`SPI_IF_bp] <= 1'b0;
endcase
end
else if(charreceivedp != charreceivedn)
begin
STATUS[`SPI_IF_bp] <= 1'b1;
charreceivedn <= ~charreceivedn;
end
end
always @ (*)
begin
bus_out <= 8'bz;
if(rd_int)
begin
case(addr[2:0])
`SPI_CTRL: bus_out <= CTRL;
`SPI_INTCTRL: bus_out <= INTCTRL;
`SPI_STATUS: bus_out <= STATUS;
`SPI_DATA: bus_out <= output_buffer;
endcase
end
end
assign int = INTCTRL[`SPI_INTLVL_gp + 1: `SPI_INTLVL_gp] ? STATUS[`SPI_IF_bp] : 1'b0;
/***********************************************/
/************ !Asynchronus send ****************/
/***********************************************/
localparam state_idle = 1'b0;
localparam state_busy = 1'b1;
reg state;
reg [PRESCALLER_SIZE - 1:0]prescaller_cnt;
reg [WORD_LEN - 1:0]shift_reg_out;
reg [WORD_LEN - 1:0]shift_reg_in;
reg [4:0]sckint;
//reg sckintn;
reg [2:0]prescallerint;
reg [7:0]prescdemux;
always @ (*)
begin
case(prescallerint)
3'b000: prescdemux <= 3;
3'b001: prescdemux <= 15;
3'b010: prescdemux <= 63;
3'b011: prescdemux <= 127;
3'b100: prescdemux <= 1;
3'b101: prescdemux <= 7;
3'b110: prescdemux <= 31;
3'b111: prescdemux <= 63;
endcase
end
reg lsbfirstint;
reg [1:0]modeint;
always @ (posedge clk or posedge rst)
begin
if(rst)
begin
baud_cnt = 'h00;
inbufffulln <= 1'b0;
ss <= 1'b1;
state <= state_idle;
prescaller_cnt <= {PRESCALLER_SIZE{1'b0}};
prescallerint <= {PRESCALLER_SIZE{3'b0}};
shift_reg_out <= {WORD_LEN{1'b0}};
shift_reg_in <= {WORD_LEN{1'b0}};
sckint <= {5{1'b0}};
_mosi <= 1'b1;
output_buffer <= {WORD_LEN{1'b0}};
charreceivedp <= 1'b0;
lsbfirstint <= 1'b0;
modeint <= 2'b00;
end
else
begin
if(DINAMIC_BAUDRATE == "TRUE" ? baud_cnt == BAUD : baud_cnt == {BAUDRATE_DIVIDER})
if(CTRL[`SPI_ENABLE_bp])
begin
if(DINAMIC_BAUDRATE == "TRUE" ? baud_cnt == prescdemux : baud_cnt == {BAUDRATE_DIVIDER})
begin
baud_cnt <= 'h00;
if(CTRL[`SPI_ENABLE_bp])
case(state)
state_idle:
begin
if(inbufffullp != inbufffulln)
begin
inbufffulln <= ~inbufffulln;
ss <= 1'b0;
prescaller_cnt <= {PRESCALLER_SIZE{1'b0}};
prescallerint <= prescallerbuff;
lsbfirstint <= CTRL[`SPI_DORD_bp];
modeint <= CTRL[`SPI_MODE_gp + 1:`SPI_MODE_gp];
shift_reg_out <= input_buffer;
state <= state_busy;
if(!CTRL[`SPI_MODE_gp])
begin
if(!CTRL[`SPI_DORD_bp])
_mosi <= input_buffer[WORD_LEN - 1];
else
_mosi <= input_buffer[0];
end
end
end
state_busy:
begin
if(prescaller_cnt != prescdemux)
begin
prescaller_cnt <= prescaller_cnt + 1;
end
else
begin
prescaller_cnt <= {PRESCALLER_SIZE{1'b0}};
sckint <= sckint + 1;
if(sckint[0] == modeint[0])
begin
if(!lsbfirstint)
begin
shift_reg_in <= {miso, shift_reg_in[7:1]};
shift_reg_out <= {shift_reg_out[6:0], 1'b1};
end
else
begin
shift_reg_in <= {shift_reg_in[6:0], miso};
shift_reg_out <= {1'b1, shift_reg_out[7:1]};
end
end
else
begin
if(sckint[4:1] == WORD_LEN - 1)
begin
sckint <= {5{1'b0}};
if(inbufffullp == inbufffulln)
begin
ss <= 1'b1;
end
output_buffer <= shift_reg_in;
if(charreceivedp == charreceivedn)
begin
charreceivedp <= ~charreceivedp;
end
state <= state_idle;
end
else
begin
if(!lsbfirstint)
_mosi <= shift_reg_out[WORD_LEN - 1];
else
_mosi <= shift_reg_out[0];
end
end
end
end
endcase
end
else
begin
baud_cnt <= baud_cnt + 1;
end
end
else
begin
baud_cnt <= baud_cnt + 1;
end
end
end
assign sck = (modeint[1])? ~sckint : sckint;
assign mosi = (ss) ? 1'b1:_mosi;
endmodule
This diff is collapsed.
......@@ -106,10 +106,14 @@ wire rtc_int;
wire int_pio_a;
wire int_pio_b;
wire int_pio_c;
wire int_pio_d;
wire int_pio_e;
wire int_pio_f;
wire int_uart_a_rx_rcv;
wire int_uart_a_tx_compl;
wire int_uart_a_tx_buff_empty;
wire [6:0]int_rst;
wire int_spi_a;
wire [10:0]int_rst;
rtc_s # (
.ADDRESS('h40),
......@@ -226,6 +230,30 @@ uart_s # (
.rx(UART_RXD)
);
wire oled_sclk;
wire oled_sdin;
spi_s #(
.DINAMIC_BAUDRATE("TRUE"),
.BAUDRATE_DIVIDER(8),
.ADDRESS('h600),
.BUS_ADDR_DATA_LEN(`BUS_ADDR_DATA_LEN_SIM)
)spi_A(
.rst(sys_rst),
.clk(core_clk),
.addr(data_addr),
.wr(data_we),
.rd(data_re),
.bus_in(data_out),
.bus_out(data_in),
.int(int_spi_a),
.sck(oled_sclk),/* SPI 'sck' signal (output) */
.mosi(oled_sdin),/* SPI 'mosi' signal (output) */
.miso(1'b1),/* SPI 'miso' signal (input) */
.ss()/* SPI 'ss' signal (if send buffer is maintained full the ss signal will not go high between between transmit chars)(output) */
);
wire lcd_h_int;
wire lcd_v_int;
wire lcd_de;
......@@ -368,7 +396,7 @@ mega_core #(
.BUS_ADDR_DATA_WIDTH(`BUS_ADDR_DATA_LEN_SIM),
.USE_BRAM_ROM("FALSE"),
.WATCHDOG_CNT_WIDTH(21),/* If is 0 the watchdog is disabled */
.VECTOR_INT_TABLE_SIZE(7),
.VECTOR_INT_TABLE_SIZE(10),
.STORE_INTERUPTS("FALSE"),
.MAP_REGS_IN_TO_SRAM_SECTION("FALSE")
)core(
......@@ -392,7 +420,7 @@ mega_core #(
.io_in(io_in),
.io_out(io_out),
.int_sig({int_uart_a_tx_buff_empty, int_uart_a_tx_compl, int_uart_a_rx_rcv, int_pio_c, int_pio_b, int_pio_a, rtc_int}),
.int_sig({int_uart_a_tx_buff_empty, int_uart_a_tx_compl, int_uart_a_rx_rcv, int_spi_a, int_pio_f, int_pio_e, int_pio_d, int_pio_c, int_pio_b, int_pio_a, rtc_int}),
.int_rst(int_rst),
.wdt_rst_out()
);
......