Commit b11ffd0a authored by Iulian Gheorghiu's avatar Iulian Gheorghiu

Begin to add support for a 2D LCD accelerator.

parent 6abf1aee
/*----------------------------------------------------------------------------/
/ This IP is a Graphic 2D accelerator interface. /
/-----------------------------------------------------------------------------/
/
/ Copyright (C) 2018 Iulian Gheorghiu (morgoth.creator@gmail.com), all right reserved.
/
/ This IP file is an open source software. Redistribution and use of this IP in
/ source and binary forms, with or without modification, are permitted provided
/ that the following condition is met:
/ 1. Redistributions of source code must retain the above copyright notice,
/ this condition and the following disclaimer.
/
/ This software is provided by the copyright holder and contributors "AS IS"
/ and any warranties related to this software are DISCLAIMED.
/ The copyright owner or contributors be NOT LIABLE for any damages caused
/ by use of this software.
/----------------------------------------------------------------------------*/
`timescale 1ns / 1ps
`include "io_s_h.v"
module gfx_to_lcd_accel #(
parameter DEBUG = "PATERN_RASTER",//"PATERN_RASTER"
parameter ADDRESS = 0,
parameter BUS_VRAM_ADDR_LEN = 24,
parameter BUS_VRAM_DATA_LEN = 8,
parameter BUS_ADDR_DATA_LEN = 16,
parameter DINAMIC_CONFIG = "FALSE",
parameter H_RES_CONF = 800,
parameter H_PULSE_WIDTH_CONF = 2,
parameter H_BLANKING_CONF = 46,
parameter H_FRONT_PORCH_CONF = 210,
parameter V_RES_CONF = 480,
parameter V_PULSE_WIDTH_CONF = 2,
parameter V_BLANKING_CONF = 23,
parameter V_FRONT_PORCH_CONF = 22,
parameter PIXEL_SIZE_CONF = 16,
parameter HSYNK_INVERTED_CONF = 1'b1,
parameter VSYNK_INVERTED_CONF = 1'b1,
parameter DATA_ENABLE_INVERTED_CONF = 1'b0,
parameter DEDICATED_VRAM_SIZE = 0
)(
input rst,
input ctrl_clk,
input [BUS_ADDR_DATA_LEN-1:0]ctrl_addr,
input ctrl_wr,
input ctrl_rd,
input [7:0]ctrl_data_in,
output [7:0]ctrl_data_out,
inout [BUS_VRAM_ADDR_LEN-1:0]vmem_addr,
input [BUS_VRAM_DATA_LEN-1:0]vmem_in,
output [BUS_VRAM_DATA_LEN-1:0]vmem_out,
input vmem_rd,
input vmem_wr,
output lcd_clk,
output lcd_h_synk,
output lcd_v_synk,
output [7:0]lcd_r,
output [7:0]lcd_g,
output [7:0]lcd_b,
output lcd_data_enable
);
lcd # (
.MASTER("FALSE"),
.DEBUG(DEBUG),
.ADDRESS(ADDRESS),
.BUS_VRAM_ADDR_LEN(BUS_VRAM_ADDR_LEN),
.BUS_VRAM_DATA_LEN(BUS_VRAM_DATA_LEN),
.BUS_ADDR_DATA_LEN(BUS_ADDR_DATA_LEN),
.DINAMIC_CONFIG(DINAMIC_CONFIG),
.VRAM_BASE_ADDRESS_CONF(0),
.H_RES_CONF(H_RES_CONF),
.H_PULSE_WIDTH_CONF(H_PULSE_WIDTH_CONF),
.H_BLANKING_CONF(H_BLANKING_CONF),
.H_FRONT_PORCH_CONF(H_FRONT_PORCH_CONF),
.V_RES_CONF(V_RES_CONF),
.V_PULSE_WIDTH_CONF(V_PULSE_WIDTH_CONF),
.V_BLANKING_CONF(V_BLANKING_CONF),
.V_FRONT_PORCH_CONF(V_FRONT_PORCH_CONF),
.PIXEL_SIZE_CONF(PIXEL_SIZE_CONF),
.DEDICATED_VRAM_SIZE(DEDICATED_VRAM_SIZE)
)lcd_inst(
.rst(rst),
.ctrl_clk(ctrl_clk),
.ctrl_addr(ctrl_addr),
.ctrl_wr(ctrl_wr),
.ctrl_rd(ctrl_rd),
.ctrl_data_in(ctrl_data_in),
.ctrl_data_out(ctrl_data_out),
.vmem_addr(vmem_addr),
.vmem_in(vmem_in),
.vmem_out(vmem_out),
.vmem_rd(vmem_rd),
.vmem_wr(vmem_wr),
.lcd_clk(lcd_clk),
.lcd_h_synk(lcd_h_synk),
.lcd_v_synk(lcd_v_synk),
.lcd_r(lcd_r),
.lcd_g(lcd_g),
.lcd_b(lcd_b),
.lcd_data_enable(lcd_data_enable)
);
endmodule
\ No newline at end of file
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