Commit aeb1fe44 authored by Iulian Gheorghiu's avatar Iulian Gheorghiu

Try to continue the DDR3 IP

parent f690b3c3
......@@ -19,7 +19,7 @@
*/
`timescale 1ns / 1ps
`include "ddr3_v.v"
/* For Attiny 26 */
//`define BUS_ADDR_PGM_LEN_SIM 11 /* < in address lines 2KWords */
//`define BUS_ADDR_DATA_LEN_SIM 8 /* < in address lines 256Bytes data address space */
......@@ -27,16 +27,26 @@
//`define DATA_ADDR_RESERVED_AT_BOTTOM_SIM 'd128 /* < in bytes ( 128 bytes to let space for IO usage )*/
/* For ATXmega */
`define BUS_ADDR_PGM_LEN_SIM 13 /* < in address lines 8KWords */
`define BUS_ADDR_DATA_LEN_SIM 14 /* < in address lines 16KBytes data address space */
`define DATA_MEM_SIZE_LEN_SIM 10 /* < in address lines 1KByte */
`define BUS_ADDR_PGM_LEN_SIM 16 /* < in address lines 8KWords */
`define BUS_ADDR_DATA_LEN_SIM 16 /* < in address lines 16KBytes data address space */
`define DATA_MEM_SIZE_LEN_SIM 12 /* < in address lines 1KByte */
`define DATA_ADDR_RESERVED_AT_BOTTOM_SIM 'd8192 /* < in bytes ( 8192 bytes is the standard atxmega reserved address for IO usage )*/
`define USE_HDMI_OUTPUT
`define DDR3_ADDR_BUS_LEN 15
module sim_uc(
`DDR3_TOP
);
`DDR3_IO
reg rst = 0;
/*ddr3 ddr3_inst(
`DDR3_CONNECT
);*/
reg int1 = 0;
reg int2 = 0;
reg int3 = 0;
......@@ -63,7 +73,6 @@ wire [2:0]hdmi_tx_p;
reg rst = 0;
reg core_clk = 0;
reg ram_clk = 0;
always #(1) ram_clk <= ~ram_clk; // clocking device
......
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