Commit 95b678d7 authored by Iulian Gheorghiu's avatar Iulian Gheorghiu

Delete old SPI, UART, PIO and TWI IP files

parent f45cea42
This diff is collapsed.
/*
* This IP is the Atmel I2C adaptor implementation.
*
* Copyright (C) 2017 Iulian Gheorghiu
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version 2
* of the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
*/
`timescale 1ns / 1ps
module i2c(
);
endmodule
/*
* This IP is the Atmel SPI adaptor implementation.
*
* Copyright (C) 2017 Iulian Gheorghiu
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version 2
* of the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
*/
`timescale 1ns / 1ps
`include "io.v"
module spi # (
parameter USE_INT = 0
)(
input rst,
input clk,
input cs,
input [1:0]offset,
input wr,
input rd,
output reg [2:0]int,
input [7:0]bus_in,
output[7:0]bus_out,
output sck,/* SPI 'sck' signal (output) */
output mosi,/* SPI 'mosi' signal (output) */
input miso,/* SPI 'miso' signal (input) */
output reg ss/* SPI 'ss' signal (if send buffer is maintained full the ss signal will not go high between between transmit chars)(output) */
);
reg [7:0]bus_out_int;
wire buffempty;
reg [7:0]CTRL;
reg [7:0]INTCTRL;
reg [7:0]STATUS;
localparam WORD_LEN = 8;
localparam PRESCALLER_SIZE = 8;
reg _mosi;
reg charreceivedp;
reg charreceivedn;
reg inbufffullp = 1'b0;
reg inbufffulln = 1'b0;
reg [WORD_LEN - 1:0]input_buffer;
reg [WORD_LEN - 1:0]output_buffer;
assign buffempty = ~(inbufffullp ^ inbufffulln);
reg [2:0]prescallerbuff;
always @ (posedge clk)
begin
if(rst)
begin
charreceivedn <= 1'b0;
inbufffullp <= 1'b0;
prescallerbuff <= 3'b000;
CTRL <= 0;
INTCTRL <= 0;
STATUS <= 0;
input_buffer <= 0;
end
else
begin
if(cs && wr && ~rd)
begin
case(offset)
`SPI_CTRL: CTRL <= bus_in;
`SPI_INTCTRL: INTCTRL <= bus_in;
`SPI_STATUS: STATUS <= STATUS ^ bus_in;
`SPI_DATA:
begin
if(inbufffullp == inbufffulln && buffempty)
begin
inbufffullp <= ~inbufffullp;
prescallerbuff <= {CTRL[7], CTRL[1:0]};
input_buffer <= bus_in;
STATUS[7] <= 1'b0;
end
end
endcase
end
else if(charreceivedp != charreceivedn)
begin
charreceivedn <= ~charreceivedn;
STATUS[7] <= 1'b1;
end
end
end
always @ (*)
begin
bus_out_int <= 8'bz;
if(cs && rd && ~wr)
begin
case(offset)
`SPI_CTRL: bus_out_int <= CTRL;
`SPI_INTCTRL: bus_out_int <= INTCTRL;
`SPI_STATUS: bus_out_int <= STATUS;
`SPI_DATA: bus_out_int <= output_buffer;
endcase
end
end
/***********************************************/
/************ !Asynchronus send ****************/
/***********************************************/
localparam state_idle = 1'b0;
localparam state_busy = 1'b1;
reg state;
reg [PRESCALLER_SIZE - 1:0]prescaller_cnt;
reg [WORD_LEN - 1:0]shift_reg_out;
reg [WORD_LEN - 1:0]shift_reg_in;
reg [4:0]sckint;
//reg sckintn;
reg [2:0]prescallerint;
reg [7:0]prescdemux;
always @ (*)
begin
if(prescallerint < PRESCALLER_SIZE)
begin
case(prescallerint)
3'b000: prescdemux <= 3;
3'b001: prescdemux <= 15;
3'b010: prescdemux <= 63;
3'b011: prescdemux <= 127;
3'b100: prescdemux <= 1;
3'b101: prescdemux <= 7;
3'b110: prescdemux <= 31;
3'b111: prescdemux <= 63;
endcase
end
else
prescdemux <= 8'b00000001;
end
reg lsbfirstint;
reg [1:0]modeint;
always @ (posedge clk or posedge rst)
begin
if(rst)
begin
inbufffulln <= 1'b0;
ss <= 1'b1;
state <= state_idle;
prescaller_cnt <= {PRESCALLER_SIZE{1'b0}};
prescallerint <= {PRESCALLER_SIZE{3'b0}};
shift_reg_out <= {WORD_LEN{1'b0}};
shift_reg_in <= {WORD_LEN{1'b0}};
sckint <= {5{1'b0}};
_mosi <= 1'b1;
output_buffer <= {WORD_LEN{1'b0}};
charreceivedp <= 1'b0;
lsbfirstint <= 1'b0;
modeint <= 2'b00;
end
else
begin
case(state)
state_idle:
begin
if(inbufffullp != inbufffulln)
begin
inbufffulln <= ~inbufffulln;
ss <= 1'b0;
prescaller_cnt <= {PRESCALLER_SIZE{1'b0}};
prescallerint <= prescallerbuff;
lsbfirstint <= CTRL[5];
modeint <= CTRL[3:2];
shift_reg_out <= input_buffer;
state <= state_busy;
if(!CTRL[2])
begin
if(!CTRL[5])
_mosi <= input_buffer[WORD_LEN - 1];
else
_mosi <= input_buffer[0];
end
end
end
state_busy:
begin
if(prescaller_cnt != prescdemux)
begin
prescaller_cnt <= prescaller_cnt + 1;
end
else
begin
prescaller_cnt <= {PRESCALLER_SIZE{1'b0}};
sckint <= sckint + 1;
if(sckint[0] == modeint[0])
begin
if(!lsbfirstint)
begin
shift_reg_in <= {miso, shift_reg_in[7:1]};
shift_reg_out <= {shift_reg_out[6:0], 1'b1};
end
else
begin
shift_reg_in <= {shift_reg_in[6:0], miso};
shift_reg_out <= {1'b1, shift_reg_out[7:1]};
end
end
else
begin
if(sckint[4:1] == WORD_LEN - 1)
begin
sckint <= {5{1'b0}};
if(inbufffullp == inbufffulln)
begin
ss <= 1'b1;
end
output_buffer <= shift_reg_in;
if(charreceivedp == charreceivedn)
begin
charreceivedp <= ~charreceivedp;
end
state <= state_idle;
end
else
begin
if(!lsbfirstint)
_mosi <= shift_reg_out[WORD_LEN - 1];
else
_mosi <= shift_reg_out[0];
end
end
end
end
endcase
end
end
always @ (*)
begin
if(USE_INT)
begin
if(STATUS)
begin
case(INTCTRL[1:0])
1: int <= 3'b001;
2: int <= 3'b010;
3: int <= 3'b100;
endcase
end
else
begin
int <= 0;
end
end
end
assign bus_out = (offset == `SPI_DATA && cs && ~wr && rd) ? output_buffer : {WORD_LEN{1'bz}};
assign sck = (modeint[1])? ~sckint : sckint;
assign mosi = (ss) ? 1'b1:_mosi;
assign bus_out = bus_out_int;
endmodule
This diff is collapsed.
/*
* This IP is the Atmel PIO adaptor implementation.
*
* Copyright (C) 2017 Iulian Gheorghiu
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version 2
* of the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
*/
`timescale 1ns / 1ps
`include "io.v"
module pio # (
parameter USE_INT = 0
)(
input rst,
input clk,
input cs,
input [4:0]offset,
input wr,
input rd,
output reg [2:0]int,
input [7:0]bus_in,
output reg[7:0]bus_out,
inout [7:0]io
);
reg [7:0]DIR;
reg [7:0]OUT;
reg [7:0]INTCTRL;
reg [7:0]INTMASK;
reg [7:0]INTFLAGS;
reg [7:0]IN_old;
reg [7:0]PINCTL[0:7];
integer intcnt;
always @ (posedge clk)
begin
if(rst)
begin
DIR <= 0;
OUT <= 0;
INTMASK <= 0;
INTFLAGS <= 0;
for(intcnt = 0; intcnt < 8; intcnt = intcnt + 1)
begin
PINCTL[intcnt] <= 0;
end
end
else
begin
if(cs && wr && ~rd)
begin
if(!offset[4])
begin
case(offset)
`PORT_DIR: DIR <= bus_in;
`PORT_OUT: OUT <= bus_in;
`PORT_INTFLAGS: INTFLAGS <= INTFLAGS ^ bus_in;
endcase
end
else if(offset[4:3] == 2'b10)
begin
PINCTL[offset[3:0]] <= bus_in;
end
end
else
begin
if(USE_INT)
begin
for(intcnt = 0; intcnt < 8; intcnt = intcnt + 1)
begin
if(PINCTL[intcnt][2:0] != `PORT_ISC_INPUT_DISABLE_gc)
begin
if(PINCTL[intcnt][2:0] == `PORT_ISC_LEVEL_gc)
begin
if(~io[intcnt])
begin
INTFLAGS[intcnt] <= 1'b1;
end
end
else
begin
if(IN_old[intcnt] != io[intcnt])
begin
IN_old[intcnt] <= io[intcnt];
if(PINCTL[intcnt][2:0] == `PORT_ISC_RISING_gc && io[intcnt])
begin
INTFLAGS[intcnt] <= 1'b1;
end
else if(PINCTL[intcnt][2:0] == `PORT_ISC_FALLING_gc && ~io[intcnt])
begin
INTFLAGS[intcnt] <= 1'b1;
end
end
end
end
end
end
end
end
end
always @ (*)
begin
if(USE_INT)
begin
if(INTFLAGS)
begin
case(INTCTRL[1:0])
1: int <= 3'b001;
2: int <= 3'b010;
3: int <= 3'b100;
endcase
end
else
begin
int <= 0;
end
end
end
genvar cnt;
generate
for (cnt = 0; cnt < 8; cnt = cnt + 1)
begin:INPUTS
/*wire kepper;
wire down;
wire up;
KEEPER KEEPER_inst (
.O(kepper)// Keeper output (connect directly to top-level port)
);
PULLDOWN PULLDOWN_inst (
.O(down)// Pulldown output (connect directly to top-level port)
);
PULLUP PULLUP_inst (
.O(up)// Pullup output (connect directly to top-level port)
);
*/
assign io[cnt] = DIR[cnt] ? OUT[cnt]/* :
(PINCTL[cnt][6:4] == `PORT_OPC_BUSKEEPER_gc >> 3) ? kepper :
(PINCTL[cnt][6:4] == `PORT_OPC_PULLDOWN_gc >> 3) ? down :
(PINCTL[cnt][6:4] == `PORT_OPC_PULLUP_gc >> 3) ? up*/ : 1'bz;
end
endgenerate
always @ (*)
begin
if(cs && rd && ~wr)
begin
case(offset)
`PORT_OUT: bus_out <= OUT;
`PORT_DIR: bus_out <= DIR;
`PORT_IN: bus_out <= io;
`PORT_INTFLAGS: bus_out <= INTFLAGS;
16: bus_out <= PINCTL[0];
17: bus_out <= PINCTL[1];
18: bus_out <= PINCTL[2];
19: bus_out <= PINCTL[3];
20: bus_out <= PINCTL[4];
21: bus_out <= PINCTL[5];
22: bus_out <= PINCTL[6];
23: bus_out <= PINCTL[7];
default: bus_out <= 8'bz;
endcase
end
else
begin
bus_out <= 8'bz;
end
end
/*assign bus = (cs && rd && ~wr) ? ((offset == `PORT_OUT) ? OUT :
(offset == `PORT_DIR) ? DIR :
(offset == `PORT_IN) ? io :
(offset == `PORT_INTFLAGS) ? INTFLAGS :
(offset == 16) ? PINCTL[0] :
(offset == 17) ? PINCTL[1] :
(offset == 18) ? PINCTL[2] :
(offset == 19) ? PINCTL[3] :
(offset == 20) ? PINCTL[4] :
(offset == 21) ? PINCTL[5] :
(offset == 22) ? PINCTL[6] :
(offset == 23) ? PINCTL[7] :
8'bz) : 8'bz;*/
endmodule
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