Commit 76990fc8 authored by Iulian Gheorghiu's avatar Iulian Gheorghiu

Add simulation support for LCD and HDMI IP's.

parent d7208e45
......@@ -32,6 +32,8 @@
`define DATA_MEM_SIZE_LEN_SIM 10 /* < in address lines 1KByte */
`define DATA_ADDR_RESERVED_AT_BOTTOM_SIM 'd8192 /* < in bytes ( 8192 bytes is the standard atxmega reserved address for IO usage )*/
`define USE_HDMI_OUTPUT
module sim_uc(
);
......@@ -50,6 +52,16 @@ wire [7:0]port_in = port_out;
wire UART_TXD;
wire UART_RXD = UART_TXD;
wire hdmi_tx_cec;
wire hdmi_tx_clk_n;
wire hdmi_tx_clk_p;
wire hdmi_tx_hpd;
wire hdmi_tx_rscl;
wire hdmi_tx_rsda;
wire [2:0]hdmi_tx_n;
wire [2:0]hdmi_tx_p;
reg rst = 0;
reg core_clk = 0;
......@@ -59,6 +71,8 @@ always @ (posedge ram_clk)
begin
core_clk <= ~core_clk;
end
wire lcd_clk = core_clk;
//wire pgm_re;
wire [`BUS_ADDR_PGM_LEN_SIM-1:0] pgm_addr;
wire [15:0] pgm_data;
......@@ -203,6 +217,112 @@ uart_s # (
.rx(UART_RXD)
);
wire lcd_h_int;
wire lcd_v_int;
wire lcd_de;
wire [7:0]ja_int;
wire [7:0]jb_int;
wire [7:0]jc_int;
wire lcd_clk_10;
`ifndef USE_HDMI_OUTPUT
assign ja = {ja_int[7:1], lcd_clk_10};
assign jb = {jb_int[7:1], lcd_h_int};
assign jc = {jc_int[7:1], lcd_v_int};
`endif
lcd # (
.MASTER("TRUE"),
.DEBUG(""),//"PATERN_RASTER"
.ADDRESS('hE0),
.BUS_VRAM_ADDR_LEN(24),
.BUS_VRAM_DATA_LEN(8),
.BUS_ADDR_DATA_LEN(16),
.DINAMIC_CONFIG("FALSE"),
.VRAM_BASE_ADDRESS_CONF(0),
`ifndef USE_HDMI_OUTPUT
/* LCD */
.H_RES_CONF(800),
.H_PULSE_WIDTH_CONF(2),
.H_BLANKING_CONF(46),
.H_FRONT_PORCH_CONF(210),
.V_RES_CONF(480),
.V_PULSE_WIDTH_CONF(2),
.V_BLANKING_CONF(23),
.V_FRONT_PORCH_CONF(22),
.PIXEL_SIZE_CONF(16),
.HSYNK_INVERTED_CONF(1'b1),
.VSYNK_INVERTED_CONF(1'b1),
.DATA_ENABLE_INVERTED_CONF(1'b0),
`else
/* HDMI */
.H_RES_CONF(720),
.H_PULSE_WIDTH_CONF(62),
.H_BLANKING_CONF(138),
.H_FRONT_PORCH_CONF(16),
.V_RES_CONF(480),
.V_PULSE_WIDTH_CONF(6),
.V_BLANKING_CONF(45),
.V_FRONT_PORCH_CONF(9),
.PIXEL_SIZE_CONF(16),
.HSYNK_INVERTED_CONF(1'b0),
.VSYNK_INVERTED_CONF(1'b0),
.DATA_ENABLE_INVERTED_CONF(1'b0),
`endif
.DEDICATED_VRAM_SIZE(800 * 480)
)lcd_inst(
.rst(sys_rst),
.ctrl_clk(core_clk),
.ctrl_addr(data_addr),
.ctrl_wr(data_we),
.ctrl_rd(data_re),
.ctrl_data_in(data_out),
.ctrl_data_out(data_in),
.vmem_addr(ram_addr_bus),
.vmem_in(data_out),
.vmem_out(data_in),
.vmem_rd(1'b0),
.vmem_wr(data_we & ram_data_sel),
`ifdef USE_HDMI_OUTPUT
.lcd_clk(lcd_clk_10),
`else
.lcd_clk(lcd_clk),
`endif
.lcd_h_synk(lcd_h_int),
.lcd_v_synk(lcd_v_int),
.lcd_r(ja_int),
.lcd_g(jb_int),
.lcd_b(jc_int),
.lcd_de(lcd_de)
);
`ifdef USE_HDMI_OUTPUT
hdmi_out hdmi_out_inst(
.rst(sys_rst),
.clk(lcd_clk),
.hdmi_tx_cec(hdmi_tx_cec),
.hdmi_tx_clk_n(hdmi_tx_clk_n),
.hdmi_tx_clk_p(hdmi_tx_clk_p),
.hdmi_tx_hpd(hdmi_tx_hpd),
.hdmi_tx_rscl(hdmi_tx_rscl),
.hdmi_tx_rsda(hdmi_tx_rsda),
.hdmi_tx_n(hdmi_tx_n),
.hdmi_tx_p(hdmi_tx_p),
.lcd_clk_out(lcd_clk_10),
.lcd_h_synk(lcd_h_int),
.lcd_v_synk(lcd_v_int),
.lcd_r('hAA),
.lcd_g('hDB),
.lcd_b('h24),
.lcd_de(lcd_de)
);
`endif
initial begin
rst = 0;
#1;
......
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