Commit 6abf1aee authored by Iulian Gheorghiu's avatar Iulian Gheorghiu

Add readme for HDMI IP.

parent 6fb20b0d
# Verilog HDMI output IP.
This is a very simple HDMI output IP that is driven by a LCD IP.
Is accepting RGB 8 bit each color, vertical and horizontal synchronization, data enable and a reference clock that is 10x the LCD clock.
The outputs are the three serial channels the clock channel and the LCD clock that is equal to reference clock / 10.
The LCD clock provided by the HDMI IP is used to clocking the LCD IP.
The RGB and sinchronization signals are provided by an LCD IP.
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