Commit 43a28433 authored by Iulian Gheorghiu's avatar Iulian Gheorghiu

Add all definition of the SPI interface for compatibility with Xmega E5 device.

parent 12948639
......@@ -578,45 +578,50 @@ SPI - Serial Peripheral Interface
`define CTRLB 4 /* Control Register B */
/* SPI Mode */
`define SPI_MODE_0_gc (8'h00<<2) /* SPI Mode 0 */
`define SPI_MODE_1_gc (8'h01<<2) /* SPI Mode 1 */
`define SPI_MODE_2_gc (8'h02<<2) /* SPI Mode 2 */
`define SPI_MODE_3_gc (8'h03<<2) /* SPI Mode 3 */
`define SPI_MODE_0_gc = (0x00<<2) /* SPI Mode 0, base clock at "0", sampling on leading edge (rising) & set-up on trailling edge (falling). */
`define SPI_MODE_1_gc = (0x01<<2) /* SPI Mode 1, base clock at "0", set-up on leading edge (rising) & sampling on trailling edge (falling). */
`define SPI_MODE_2_gc = (0x02<<2) /* SPI Mode 2, base clock at "1", sampling on leading edge (falling) & set-up on trailling edge (rising). */
`define SPI_MODE_3_gc = (0x03<<2) /* SPI Mode 3, base clock at "1", set-up on leading edge (falling) & sampling on trailling edge (rising). */
/* Prescaler setting */
`define SPI_PRESCALER_DIV4_gc (8'h00<<0) /* System Clock / 4 */
`define SPI_PRESCALER_DIV16_gc (8'h01<<0) /* System Clock / 16 */
`define SPI_PRESCALER_DIV64_gc (8'h02<<0) /* System Clock / 64 */
`define SPI_PRESCALER_DIV128_gc (8'h03<<0) /* System Clock / 128 */
`define SPI_PRESCALER_DIV4_gc = (0x00<<0) /* If CLK2X=1 CLKper/2, else (CLK2X=0) CLKper/4. */
`define SPI_PRESCALER_DIV16_gc = (0x01<<0) /* If CLK2X=1 CLKper/8, else (CLK2X=0) CLKper/16. */
`define SPI_PRESCALER_DIV64_gc = (0x02<<0) /* If CLK2X=1 CLKper/32, else (CLK2X=0) CLKper/64. */
`define SPI_PRESCALER_DIV128_gc = (0x03<<0) /* If CLK2X=1 CLKper/64, else (CLK2X=0) CLKper/128. */
/* Interrupt level */
`define SPI_INTLVL_OFF_gc (8'h00<<0) /* Interrupt Disabled */
`define SPI_INTLVL_LO_gc (8'h01<<0) /* Low Level */
`define SPI_INTLVL_MED_gc (8'h02<<0) /* Medium Level */
`define SPI_INTLVL_HI_gc (8'h03<<0) /* High Level */
`define SPI_INTLVL_OFF_gc = (0x00<<0) /* Interrupt Disabled */
`define SPI_INTLVL_LO_gc = (0x01<<0) /* Low Level */
`define SPI_INTLVL_MED_gc = (0x02<<0) /* Medium Level */
`define SPI_INTLVL_HI_gc = (0x03<<0) /* High Level */
/* Buffer Modes */
`define SPI_BUFMODE_OFF_gc = (0x00<<6) /* SPI Unbuffered Mode */
`define SPI_BUFMODE_BUFMODE1_gc = (0x02<<6) /* Buffer Mode 1 (with dummy byte) */
`define SPI_BUFMODE_BUFMODE2_gc = (0x03<<6) /* Buffer Mode 2 (no dummy byte) */
/* SPI - Serial Peripheral Interface */
/* SPI.CTRL bit masks and bit positions */
`define SPI_CLK2X_bm 8'h80 /* Enable Double Speed bit mask. */
`define SPI_CLK2X_bm 0x80 /* Enable Double Speed bit mask. */
`define SPI_CLK2X_bp 7 /* Enable Double Speed bit position. */
`define SPI_ENABLE_bm 8'h40 /* Enable Module bit mask. */
`define SPI_ENABLE_bp 6 /* Enable Module bit position. */
`define SPI_ENABLE_bm 0x40 /* Enable SPI Module bit mask. */
`define SPI_ENABLE_bp 6 /* Enable SPI Module bit position. */
`define SPI_DORD_bm 8'h20 /* Data Order Setting bit mask. */
`define SPI_DORD_bm 0x20 /* Data Order Setting bit mask. */
`define SPI_DORD_bp 5 /* Data Order Setting bit position. */
`define SPI_MASTER_bm 8'h10 /* Master Operation Enable bit mask. */
`define SPI_MASTER_bm 0x10 /* Master Operation Enable bit mask. */
`define SPI_MASTER_bp 4 /* Master Operation Enable bit position. */
`define SPI_MODE_gm 8'h0C /* SPI Mode group mask. */
`define SPI_MODE_gm 0x0C /* SPI Mode group mask. */
`define SPI_MODE_gp 2 /* SPI Mode group position. */
`define SPI_MODE0_bm (1<<2) /* SPI Mode bit 0 mask. */
`define SPI_MODE0_bp 2 /* SPI Mode bit 0 position. */
`define SPI_MODE1_bm (1<<3) /* SPI Mode bit 1 mask. */
`define SPI_MODE1_bp 3 /* SPI Mode bit 1 position. */
`define FPGA_SPI_MODE1_bm (1<<3) /* SPI Mode bit 1 mask. */
`define MODE1_bp 3 /* SPI Mode bit 1 position. */
`define SPI_PRESCALER_gm 8'h03 /* Prescaler group mask. */
`define SPI_PRESCALER_gm 0x03 /* Prescaler group mask. */
`define SPI_PRESCALER_gp 0 /* Prescaler group position. */
`define SPI_PRESCALER0_bm (1<<0) /* Prescaler bit 0 mask. */
`define SPI_PRESCALER0_bp 0 /* Prescaler bit 0 position. */
......@@ -624,7 +629,19 @@ SPI - Serial Peripheral Interface
`define SPI_PRESCALER1_bp 1 /* Prescaler bit 1 position. */
/* SPI.INTCTRL bit masks and bit positions */
`define SPI_INTLVL_gm 8'h03 /* Interrupt level group mask. */
`define SPI_RXCIE_bm 0x80 /* Receive Complete Interrupt Enable (In Buffer Modes Only). bit mask. */
`define SPI_RXCIE_bp 7 /* Receive Complete Interrupt Enable (In Buffer Modes Only). bit position. */
`define SPI_TXCIE_bm 0x40 /* Transmit Complete Interrupt Enable (In Buffer Modes Only). bit mask. */
`define SPI_TXCIE_bp 6 /* Transmit Complete Interrupt Enable (In Buffer Modes Only). bit position. */
`define SPI_DREIE_bm 0x20 /* Data Register Empty Interrupt Enable (In Buffer Modes Only). bit mask. */
`define SPI_DREIE_bp 5 /* Data Register Empty Interrupt Enable (In Buffer Modes Only). bit position. */
`define SPI_SSIE_bm 0x10 /* Slave Select Trigger Interrupt Enable (In Buffer Modes Only). bit mask. */
`define SPI_SSIE_bp 4 /* Slave Select Trigger Interrupt Enable (In Buffer Modes Only). bit position. */
`define SPI_INTLVL_gm 0x03 /* Interrupt level group mask. */
`define SPI_INTLVL_gp 0 /* Interrupt level group position. */
`define SPI_INTLVL0_bm (1<<0) /* Interrupt level bit 0 mask. */
`define SPI_INTLVL0_bp 0 /* Interrupt level bit 0 position. */
......@@ -632,11 +649,37 @@ SPI - Serial Peripheral Interface
`define SPI_INTLVL1_bp 1 /* Interrupt level bit 1 position. */
/* SPI.STATUS bit masks and bit positions */
`define SPI_IF_bm 8'h80 /* Interrupt Flag bit mask. */
`define SPI_IF_bp 7 /* Interrupt Flag bit position. */
`define SPI_IF_bm 0x80 /* Interrupt Flag (In Standard Mode Only). bit mask. */
`define SPI_IF_bp 7 /* Interrupt Flag (In Standard Mode Only). bit position. */
`define SPI_RXCIF_bm 0x80 /* Receive Complete Interrupt Flag (In Buffer Modes Only). bit mask. */
`define SPI_RXCIF_bp 7 /* Receive Complete Interrupt Flag (In Buffer Modes Only). bit position. */
`define SPI_WRCOL_bm 0x40 /* Write Collision Flag (In Standard Mode Only). bit mask. */
`define SPI_WRCOL_bp 6 /* Write Collision Flag (In Standard Mode Only). bit position. */
`define SPI_TXCIF_bm 0x40 /* Transmit Complete Interrupt Flag (In Buffer Modes Only). bit mask. */
`define SPI_TXCIF_bp 6 /* Transmit Complete Interrupt Flag (In Buffer Modes Only). bit position. */
`define SPI_DREIF_bm 0x20 /* Data Register Empty Interrupt Flag (In Buffer Modes Only). bit mask. */
`define SPI_DREIF_bp 5 /* Data Register Empty Interrupt Flag (In Buffer Modes Only). bit position. */
`define SPI_SSIF_bm 0x10 /* Slave Select Trigger Interrupt Flag (In Buffer Modes Only). bit mask. */
`define SPI_SSIF_bp 4 /* Slave Select Trigger Interrupt Flag (In Buffer Modes Only). bit position. */
`define SPI_BUFOVF_bm 0x01 /* Buffer Overflow (In Buffer Modes Only). bit mask. */
`define SPI_BUFOVF_bp 0 /* Buffer Overflow (In Buffer Modes Only). bit position. */
/* SPI.CTRLB bit masks and bit positions */
`define SPI_BUFMODE_gm 0xC0 /* Buffer Modes group mask. */
`define SPI_BUFMODE_gp 6 /* Buffer Modes group position. */
`define SPI_BUFMODE0_bm (1<<6) /* Buffer Modes bit 0 mask. */
`define SPI_BUFMODE0_bp 6 /* Buffer Modes bit 0 position. */
`define SPI_BUFMODE1_bm (1<<7) /* Buffer Modes bit 1 mask. */
`define SPI_BUFMODE1_bp 7 /* Buffer Modes bit 1 position. */
`define SPI_WRCOL_bm 8'h40 /* Write Collision bit mask. */
`define SPI_WRCOL_bp 6 /* Write Collision bit position. */
`define SPI_SSD_bm 0x04 /* Slave Select Disable bit mask. */
`define SPI_SSD_bp 2 /* Slave Select Disable bit position. */
/*
--------------------------------------------------------------------------
......
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