Commit 391c969a authored by Iulian Gheorghiu's avatar Iulian Gheorghiu

Add file

parent 3bef9980
# LCD interface IP.
This IP is a dinamic/parametrized LCD interface IP that generate pixel data, horizontal synchro, vertical synchro, data enable and clock reference for the LCD pannel or the HDMI IP.
At this moment has implemented only the option to use the BRAM for VRAM and a pattern used for debug that does not use any VRAM.
The IP has two busses, one for controll in case of dinamic configuration usage and one for read/write of the VRAM.
The VRAM BRAM is configured for true dualport mode, one port for read/write the data to the VRAM and one read only to feed the LCD display.
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