Commit 37cc7d17 authored by Iulian Gheorghiu's avatar Iulian Gheorghiu

Add 8bit/color mode.

Fix data_enable wire signal.
parent 398c9bc2
......@@ -102,7 +102,7 @@ reg [13:0]v_res_int;
reg [7:0]v_pulse_width_int;
reg [7:0]v_back_porch_int;
reg [7:0]v_front_porch_int;
reg [5:0]pixel_size_int;
wire [5:0]pixel_size_int = (DINAMIC_CONFIG == "TRUE") ? PIXEL_SIZE : PIXEL_SIZE_CONF;
reg hsynk_inverted_int;
reg vsynk_inverted_int;
reg data_enable_inverted_int;
......@@ -119,7 +119,6 @@ begin
v_back_porch_int = 33;
v_front_porch_int = 10;
v_pulse_width_int = 2;
pixel_size_int = 16;
hsynk_inverted_int = 0;
vsynk_inverted_int = 0;
data_enable_inverted_int= 0;
......@@ -135,7 +134,6 @@ begin
v_back_porch_int = 32;
v_front_porch_int = 10;
v_pulse_width_int = 3;
pixel_size_int = 16;
hsynk_inverted_int = 0;
vsynk_inverted_int = 0;
data_enable_inverted_int= 0;
......@@ -151,7 +149,6 @@ begin
v_back_porch_int = 30;
v_front_porch_int = 9;
v_pulse_width_int = 6;
pixel_size_int = 16;
hsynk_inverted_int = 0;
vsynk_inverted_int = 0;
data_enable_inverted_int= 0;
......@@ -167,7 +164,6 @@ begin
v_back_porch_int = 23;
v_front_porch_int = 4;
v_pulse_width_int = 5;
pixel_size_int = 16;
hsynk_inverted_int = 0;
vsynk_inverted_int = 0;
data_enable_inverted_int= 0;
......@@ -183,7 +179,6 @@ begin
v_back_porch_int = 29;
v_front_porch_int = 3;
v_pulse_width_int = 6;
pixel_size_int = 16;
hsynk_inverted_int = 0;
vsynk_inverted_int = 0;
data_enable_inverted_int= 0;
......@@ -199,7 +194,6 @@ begin
v_back_porch_int = 25;
v_front_porch_int = 3;
v_pulse_width_int = 5;
pixel_size_int = 16;
hsynk_inverted_int = 0;
vsynk_inverted_int = 0;
data_enable_inverted_int= 0;
......@@ -215,13 +209,12 @@ begin
v_back_porch_int = 21;
v_front_porch_int = 3;
v_pulse_width_int = 6;
pixel_size_int = 16;
hsynk_inverted_int = 0;
vsynk_inverted_int = 0;
data_enable_inverted_int= 0;
end
else
if(DISPLAY_CFG == "1440_900_60_DISPLAY_106_50_Mhz")
if(DISPLAY_CFG == "1440_900_60_DISPLAY_106_50_Mhz")/* Working at 100Mhz pixel clock rate on -1 grade device */
begin
h_res_int = 1440;
h_back_porch_int = 232;
......@@ -231,7 +224,6 @@ begin
v_back_porch_int = 25;
v_front_porch_int = 3;
v_pulse_width_int = 6;
pixel_size_int = 16;
hsynk_inverted_int = 0;
vsynk_inverted_int = 0;
data_enable_inverted_int= 0;
......@@ -247,7 +239,6 @@ begin
v_back_porch_int = 30;
v_front_porch_int = 3;
v_pulse_width_int = 6;
pixel_size_int = 16;
hsynk_inverted_int = 1;
vsynk_inverted_int = 0;
data_enable_inverted_int= 0;
......@@ -263,7 +254,6 @@ begin
v_back_porch_int = 40;
v_front_porch_int = 4;
v_pulse_width_int = 5;
pixel_size_int = 16;
hsynk_inverted_int = 1;
vsynk_inverted_int = 0;
data_enable_inverted_int= 0;
......@@ -279,7 +269,6 @@ begin
v_back_porch_int = 21;
v_front_porch_int = 22;
v_pulse_width_int = 2;
pixel_size_int = 16;
hsynk_inverted_int = 0;
vsynk_inverted_int = 0;
data_enable_inverted_int= 0;
......@@ -294,7 +283,6 @@ begin
v_back_porch_int = (DINAMIC_CONFIG == "TRUE") ? V_BACK_PORCH : V_BACK_PORCH_CONF;
v_front_porch_int = (DINAMIC_CONFIG == "TRUE") ? V_FRONT_PORCH : V_FRONT_PORCH_CONF;
v_pulse_width_int = (DINAMIC_CONFIG == "TRUE") ? V_PULSE_WIDTH : V_PULSE_WIDTH_CONF;
pixel_size_int = (DINAMIC_CONFIG == "TRUE") ? PIXEL_SIZE : PIXEL_SIZE_CONF;
hsynk_inverted_int = (DINAMIC_CONFIG == "TRUE") ? HSYNK_INVERTED : HSYNK_INVERTED_CONF;
vsynk_inverted_int = (DINAMIC_CONFIG == "TRUE") ? VSYNK_INVERTED : VSYNK_INVERTED_CONF;
data_enable_inverted_int= (DINAMIC_CONFIG == "TRUE") ? DATA_ENABLE_INVERTED : DATA_ENABLE_INVERTED_CONF;
......@@ -344,7 +332,7 @@ reg [PIXEL_SIZE_CONF-1:0] vmem [(DEDICATED_VRAM_SIZE ? DEDICATED_VRAM_SIZE - 1 :
/* This is an intermediary register that stores the pixel data taken from VRAM untranslated. */
reg [31:0]vmem_out_int;
/* This register will store the decoded RGB pixel data from other formats like 565. */
reg [PIXEL_SIZE_CONF-1:0]vmem_raster_int;
reg [31:0]vmem_raster_int;
/* This register is used to store most significand byte to store 16 bit configuration registry. */
reg [7:0]ctrl_write_tmp;
......@@ -446,7 +434,7 @@ begin
else
vmem[wram_addr_int] <= {vmem_in, tmp_vmem_in_2, tmp_vmem_in_1};
end
else if(BUS_VRAM_DATA_LEN == 16 && pixel_size_int == 16)
else if((BUS_VRAM_DATA_LEN == 16 && pixel_size_int == 16) || (BUS_VRAM_DATA_LEN == 8 && pixel_size_int == 8))
vmem[wram_addr_int] <= vmem_in;
else if(BUS_VRAM_DATA_LEN == 32 && pixel_size_int == 24 && PIXEL_SIZE_CONF == 24)
vmem[wram_addr_int] <= vmem_in;
......@@ -575,7 +563,13 @@ end
always @ *
begin
if(pixel_size_int == 16)
if(pixel_size_int == 8)
begin
lcd_r_int <= {vmem_raster_int[2:0], 5'h0};
lcd_g_int <= {vmem_raster_int[4:3], 6'h0};
lcd_b_int <= {vmem_raster_int[7:5], 5'h0};
end
else if(pixel_size_int == 16)
begin
lcd_r_int <= {vmem_raster_int[4:0], 3'h0};
lcd_g_int <= {vmem_raster_int[10:5], 2'h0};
......@@ -587,7 +581,7 @@ always @ *
begin
lcd_h_synk_int <= H_CNT < h_pulse_width_int;
lcd_v_synk_int <= V_CNT < v_pulse_width_int;
data_enable_int <= H_CNT >= h_pulse_width_int + h_back_porch_int && H_CNT <= h_pulse_width_int + h_back_porch_int + h_res_int && V_CNT >= h_pulse_width_int + v_back_porch_int && V_CNT <= h_pulse_width_int + h_back_porch_int + v_res_int;
data_enable_int <= H_CNT >= h_pulse_width_int + h_back_porch_int && H_CNT <= h_pulse_width_int + h_back_porch_int + h_res_int && V_CNT >= v_pulse_width_int + v_back_porch_int && V_CNT <= v_pulse_width_int + v_back_porch_int + v_res_int;
fifo_rst_int <= &(~{H_CNT, V_CNT});
end
......
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