Commit 2f10bb1a authored by Iulian Gheorghiu's avatar Iulian Gheorghiu

Move the DDR3 IP to dedicated directory

parent 1d88ea54
......@@ -77,7 +77,7 @@ begin : DQ_DES
.rst(rst),
.clk(ddr3_dqs_in[count / 8]),
.rec_en(ddr3_dq_receiver_en),
.s_in(ddr3_dq_in),
.s_in(ddr3_dq_in[count]),
.data_rec({pdata_out[count + (D_BUS_WIDTH * 7)], pdata_out[count + (D_BUS_WIDTH * 6)], pdata_out[count+ (D_BUS_WIDTH * 5)], pdata_out[count + (D_BUS_WIDTH * 4)],
pdata_out[count + (D_BUS_WIDTH * 3)], pdata_out[count + (D_BUS_WIDTH * 2)], pdata_out[count + (D_BUS_WIDTH * 1)], pdata_out[count]}),
.ready(dq_in_ready[count])
......@@ -93,7 +93,7 @@ begin : DQ_SER
.rst(rst),
.clk(clk),
.write(ddr3_pdata_write),
.s_out(ddr3_dq_out),
.s_out(ddr3_dq_out[count]),
.data_send({pdata_in[count + (D_BUS_WIDTH * 7)], pdata_in[count + (D_BUS_WIDTH * 6)], pdata_in[count+ (D_BUS_WIDTH * 5)], pdata_in[count + (D_BUS_WIDTH * 4)],
pdata_in[count + (D_BUS_WIDTH * 3)], pdata_in[count + (D_BUS_WIDTH * 2)], pdata_in[count + (D_BUS_WIDTH * 1)], pdata_in[count]}),
.ck_en_out(),
......
......@@ -21,9 +21,9 @@
`define DDR3_TOP \
output [1:0]ddr3_dm, \
inout [15:0]ddr3_dq, \
inout [13:0]ddr3_addr, \
output [1:0]ddr3_dqs_p, \
output [1:0]ddr3_dqs_n, \
inout [`DDR3_ADDR_BUS_LEN-1:0]ddr3_addr, \
inout [1:0]ddr3_dqs_p, \
inout [1:0]ddr3_dqs_n, \
output [0:0]ddr3_ck_p, \
output [0:0]ddr3_ck_n, \
output [2:0]ddr3_ba, \
......@@ -43,7 +43,7 @@ wire [15:0]ddr3_dq_in; \
wire [15:0]ddr3_dq_out; \
wire ddr3_dq_oe; \
\
wire [13:0]ddr3_addr_out; \
wire [`DDR3_ADDR_BUS_LEN-1:0]ddr3_addr_out; \
\
wire [1:0]ddr3_dqs_in; \
wire [1:0]ddr3_dqs_out; \
......@@ -87,7 +87,7 @@ IOBUF #( \
.T({16{~ddr3_dq_oe}}) // 3-state enable input, high=input, low=output \
); \
\
OBUF #(.SLEW("FAST")) OBUF_ADDR_inst [13:0]( \
OBUF #(.SLEW("FAST")) OBUF_ADDR_inst [`DDR3_ADDR_BUS_LEN-1:0]( \
.O(ddr3_addr), // Buffer output (connect directly to top-level port) \
.I(ddr3_addr_out) // Buffer input \
); \
......@@ -155,9 +155,9 @@ OBUF #(.SLEW("FAST")) OBUF_RESET_inst ( \
`define DDR3_CONNECT \
.rst(rst), \
.clk(clk_int), \
.clk90(clk90_int), \
.clkdiv(clkdiv_int), \
.clk(ddr3_clk_int), \
.clk90(ddr3_clk90_int), \
.clkdiv(ddr3_clkdiv_int), \
\
.ddr3_dm_out(ddr3_dm_out), \
\
......
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