Commit 1d88ea54 authored by Iulian Gheorghiu's avatar Iulian Gheorghiu

Fix the delay inside the "dedicated_divider_clk_5" shift register that divide…

Fix the delay inside the "dedicated_divider_clk_5" shift register that divide the reference clock by 5.
parent 37cc7d17
......@@ -144,7 +144,7 @@ begin
else
dedicated_divider_clk_5 <= {dedicated_divider_clk_5[0], dedicated_divider_clk_5[4:1]};
end
always @ * clk_5 = dedicated_divider_clk_5[0];
always @ (posedge clk) clk_5 = dedicated_divider_clk_5[0];
/* Here we do XOR,NXOR of bits and inverse of the symbol to do the bias neutral signal.*/
always @ (clk)
begin
......
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