Commit 0cb37837 authored by Iulian Gheorghiu's avatar Iulian Gheorghiu

Add MULS/MULSU/FMUL/FMULS/FMULSU instructions.

parent 43a28433
......@@ -634,7 +634,7 @@ wire [16:0] sub_result_int_w_c = sub_result_int_w_c_tmp[17:1];
reg [7:0]in_1_mul;
reg [7:0]in_2_mul;
wire [15:0]mul_result_int = in_1_mul * in_2_mul;
wire mul_sign_int = in_1 ^ in_2;
always @ (*)
begin
if(CORE_CONFIG != "REDUCED" && CORE_CONFIG != "MINIMAL" && CORE_CONFIG != "CLASSIC_8K" && CORE_CONFIG != "CLASSIC_128K")
......@@ -643,13 +643,13 @@ begin
in_2_mul <= 0;
if(SEL_INSTRUCTION_MUL | SEL_INSTRUCTION_FMUL)
begin
in_1_mul <= in_1;
in_2_mul <= in_2;
in_1_mul <= in_1[7:0];
in_2_mul <= in_2[7:0];
end
if(SEL_INSTRUCTION_MULS | SEL_INSTRUCTION_FMULS)
begin
in_1_mul <= {1'b0, in_1[6:0]};
in_2_mul <= {1'b0, in_2[6:0]} ;
in_2_mul <= {1'b0, in_2[6:0]};
end
if(SEL_INSTRUCTION_MULSU | SEL_INSTRUCTION_FMULSU)
begin
......@@ -701,16 +701,16 @@ begin
if((SEL_INSTRUCTION_MUL) && CORE_CONFIG != "REDUCED" && CORE_CONFIG != "MINIMAL" && CORE_CONFIG != "CLASSIC_8K" && CORE_CONFIG != "CLASSIC_128K")
{ALU_FLAG_C_OUT, out} <= {mul_result_int[15], mul_result_int};
if((SEL_INSTRUCTION_MULS) && CORE_CONFIG != "REDUCED" && CORE_CONFIG != "MINIMAL" && CORE_CONFIG != "CLASSIC_8K" && CORE_CONFIG != "CLASSIC_128K")
{ALU_FLAG_C_OUT, out} <= {mul_result_int[15], in_1_mul[7] ^ in_2_mul[7], mul_result_int[14:0]};
{ALU_FLAG_C_OUT, out} <= {mul_sign_int, mul_sign_int, mul_result_int[14:0]};
if((SEL_INSTRUCTION_MULSU) && CORE_CONFIG != "REDUCED" && CORE_CONFIG != "MINIMAL" && CORE_CONFIG != "CLASSIC_8K" && CORE_CONFIG != "CLASSIC_128K")
{ALU_FLAG_C_OUT, out} <= {mul_result_int[15], in_1_mul[7], mul_result_int[14:0]};
{ALU_FLAG_C_OUT, out} <= {in_1[7], in_1[7], mul_result_int};
if((SEL_INSTRUCTION_FMUL) && CORE_CONFIG != "REDUCED" && CORE_CONFIG != "MINIMAL" && CORE_CONFIG != "CLASSIC_8K" && CORE_CONFIG != "CLASSIC_128K")
{ALU_FLAG_C_OUT, out} <= {mul_result_int[15], mul_result_int[14:0], 1'b0};
if((SEL_INSTRUCTION_FMULS) && CORE_CONFIG != "REDUCED" && CORE_CONFIG != "MINIMAL" && CORE_CONFIG != "CLASSIC_8K" && CORE_CONFIG != "CLASSIC_128K")
{ALU_FLAG_C_OUT, out} <= {mul_result_int[15], in_1_mul[7] ^ in_2_mul[7], mul_result_int[13:0], 1'b0};
{ALU_FLAG_C_OUT, out} <= {mul_sign_int, mul_result_int[14:0], 1'b0};
if((SEL_INSTRUCTION_FMULSU) && CORE_CONFIG != "REDUCED" && CORE_CONFIG != "MINIMAL" && CORE_CONFIG != "CLASSIC_8K" && CORE_CONFIG != "CLASSIC_128K")
{ALU_FLAG_C_OUT, out} <= {mul_result_int[15], in_1_mul[7], mul_result_int[13:0], 1'b0};
{ALU_FLAG_C_OUT, out} <= {in_1[7], mul_result_int[14:0], 1'b0};
if(SEL_INSTRUCTION_ASR) {ALU_FLAG_C_OUT, out} <= {in_1[0], 8'h00, in_1[7], in_1[7:1]};
if(SEL_INSTRUCTION_CP |
......@@ -885,7 +885,7 @@ begin
SEL_INSTRUCTION_MULSU |
SEL_INSTRUCTION_FMULS |
SEL_INSTRUCTION_FMULSU)
ALU_FLAG_Z_OUT <= &(~out[14:0]);
ALU_FLAG_Z_OUT <= &(~out[15:0]);
end
end
......@@ -1010,7 +1010,7 @@ module mega_core # (
output reg [(VECTOR_INT_TABLE_SIZE == 0 ? 0 : VECTOR_INT_TABLE_SIZE - 1):0]int_rst,
output reg wdt_rst_out
);
reg [7:0]ALU_FLAGS = 0; //Carry Flag
wire ALU_FLAG_C_OUT; //Carry Flag
wire ALU_FLAG_Z_OUT; //Zero Flag
......@@ -1344,6 +1344,11 @@ reg SEL_S2_INSTRUCTION_JMP;
reg SEL_S2_INSTRUCTION_CALL;
reg SEL_S2_INSTRUCTION_SBIC_SBIS;
reg SEL_S2_INSTRUCTION_MUL;
reg SEL_S2_INSTRUCTION_MULS;
reg SEL_S2_INSTRUCTION_MULSU;
reg SEL_S2_INSTRUCTION_FMUL;
reg SEL_S2_INSTRUCTION_FMULS;
reg SEL_S2_INSTRUCTION_FMULSU;
reg SEL_S2_INSTRUCTION_RCALL;
reg SEL_S2_INSTRUCTION_SBRC_SBRS;
......@@ -1882,7 +1887,12 @@ begin
end
if(CORE_CONFIG != "REDUCED" && CORE_CONFIG != "MINIMAL" && CORE_CONFIG != "CLASSIC_8K" && CORE_CONFIG != "CLASSIC_128K")
begin
if(SEL_S1_INSTRUCTION_MUL)
if((SEL_S1_INSTRUCTION_MUL |
SEL_S1_INSTRUCTION_MULS |
SEL_S1_INSTRUCTION_MULSU |
SEL_S1_INSTRUCTION_FMUL |
SEL_S1_INSTRUCTION_FMULS |
SEL_S1_INSTRUCTION_FMULSU))
begin
rw_16bit <= 1'b1;
rd_addr_d <= pgm_data_int[8:4];
......@@ -2159,7 +2169,12 @@ begin
end/*!CORE_CONFIG != "REDUCED" && CORE_CONFIG != "MINIMAL"*/
if(CORE_CONFIG != "REDUCED" && CORE_CONFIG != "MINIMAL" && CORE_CONFIG != "CLASSIC_8K" && CORE_CONFIG != "CLASSIC_128K")
begin
if(SEL_S2_INSTRUCTION_MUL)
if((SEL_S2_INSTRUCTION_MUL |
SEL_S2_INSTRUCTION_MULS |
SEL_S2_INSTRUCTION_MULSU |
SEL_S2_INSTRUCTION_FMUL |
SEL_S2_INSTRUCTION_FMULS |
SEL_S2_INSTRUCTION_FMULSU))
begin
rw_16bit <= 1'b1;
rd_addr_d <= pgm_data_int[8:4];
......@@ -2267,6 +2282,11 @@ begin
SEL_S2_INSTRUCTION_CALL <= 'h0;
SEL_S2_INSTRUCTION_SBIC_SBIS <= 'h0;
SEL_S2_INSTRUCTION_MUL <= 'h0;
SEL_S2_INSTRUCTION_MULS <= 'h0;
SEL_S2_INSTRUCTION_MULSU <= 'h0;
SEL_S2_INSTRUCTION_FMUL <= 'h0;
SEL_S2_INSTRUCTION_FMULS <= 'h0;
SEL_S2_INSTRUCTION_FMULSU <= 'h0;
SEL_S2_INSTRUCTION_RCALL <= 'h0;
SEL_S2_INSTRUCTION_SBRC_SBRS <= 'h0;
PC <= 'h0000;
......@@ -2335,6 +2355,11 @@ begin
SEL_S2_INSTRUCTION_CALL <= SEL_S1_INSTRUCTION_CALL;
SEL_S2_INSTRUCTION_SBIC_SBIS <= SEL_S1_INSTRUCTION_SBIC_SBIS;
SEL_S2_INSTRUCTION_MUL <= SEL_S1_INSTRUCTION_MUL;
SEL_S2_INSTRUCTION_MULS <= SEL_S1_INSTRUCTION_MULS;
SEL_S2_INSTRUCTION_MULSU <= SEL_S1_INSTRUCTION_MULSU;
SEL_S2_INSTRUCTION_FMUL <= SEL_S1_INSTRUCTION_FMUL;
SEL_S2_INSTRUCTION_FMULS <= SEL_S1_INSTRUCTION_FMULS;
SEL_S2_INSTRUCTION_FMULSU <= SEL_S1_INSTRUCTION_FMULSU;
SEL_S2_INSTRUCTION_RCALL <= SEL_S1_INSTRUCTION_RCALL;
SEL_S2_INSTRUCTION_SBRC_SBRS <= SEL_S1_INSTRUCTION_SBRC_SBRS;
`ifdef USE_RAM_READ_DELAY
......@@ -2365,9 +2390,14 @@ begin
if(ram_read_delay == 0 &&
(SEL_S2_INSTRUCTION_LPM_R ||
SEL_S2_INSTRUCTION_LPM_R_P ||
SEL_S1_INSTRUCTION_LPM_ELPM ||
SEL_S2_INSTRUCTION_LPM_ELPM ||
(SEL_S2_INSTRUCTION_LDS_STS && ~pgm_data_int[9]) ||
(SEL_S2_INSTRUCTION_MUL && (CORE_CONFIG != "CLASSIC_8K" && CORE_CONFIG != "CLASSIC_128K")) ||
((SEL_S2_INSTRUCTION_MUL |
SEL_S2_INSTRUCTION_MULS |
SEL_S2_INSTRUCTION_MULSU |
SEL_S2_INSTRUCTION_FMUL |
SEL_S2_INSTRUCTION_FMULS |
SEL_S2_INSTRUCTION_FMULSU) && (CORE_CONFIG != "CLASSIC_8K" && CORE_CONFIG != "CLASSIC_128K")) ||
((SEL_S2_INSTRUCTION_LD_ST_YZP ||
SEL_S2_INSTRUCTION_LD_ST_YZN ||
SEL_S2_INSTRUCTION_LD_ST_X ||
......@@ -2556,7 +2586,12 @@ begin
tmp_pgm_data <= pgm_data_int;
step_cnt <= `STEP2;
end
if(SEL_S1_INSTRUCTION_MUL && (CORE_CONFIG != "CLASSIC_8K" && CORE_CONFIG != "CLASSIC_128K"))
if((SEL_S1_INSTRUCTION_MUL |
SEL_S1_INSTRUCTION_MULS |
SEL_S1_INSTRUCTION_MULSU |
SEL_S1_INSTRUCTION_FMUL |
SEL_S1_INSTRUCTION_FMULS |
SEL_S1_INSTRUCTION_FMULSU) && (CORE_CONFIG != "CLASSIC_8K" && CORE_CONFIG != "CLASSIC_128K"))
begin
tmp_pgm_data <= pgm_data_int;
step_cnt <= `STEP2;
......
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