Commit 23077ad0 authored by Iulian Gheorghiu's avatar Iulian Gheorghiu

Initial commit

parent 06e0d251
This diff is collapsed.
[General]
showNCD=true
showPgroups=true
showCongestion=false
showConnsSelect=false
showConnsBetween=true
showConnsOutside=true
showLPF=true
showREGIONs=true
showUGROUPs=true
showPARITIONs=true
showLogicalConnections=false
dontShowBBoxOverlapWarning=false
sceneInViewRect="@Variant(\0\0\0\x14\xc1\x3\x15\x96\xda\xa4=K\xc0\xec\xf2\v0\xb8\x8d\xdd\x41\x1dr]\xc3\xeJ\bA\v6\xbf\x65\xbe\xec\x8d)"
[SysIOView]
Type=100
Name=100
Pin=100
Bank=100
IO_TYPE=100
PULLMODE=100
DRIVE=100
SLEWRATE=100
CLAMP=100
OPENDRAIN=100
DIFFRESISTOR=100
DIFFDRIVE=100
BANK_VCCIO=100
HYSTERESIS=100
SortColumns="1,"
[PLLView]
Type=100
Name=100
SortColumns="2,"
[MemoryTreeView]
EBR%20Configuration=340
Setting=88
[Runmanager]
Geometry=@ByteArray(\x1\xd9\xd0\xcb\0\x1\0\0\0\0\0\0\0\0\0\0\0\0\x1\x1c\0\0\0\xd8\0\0\0\0\0\0\0\0\xff\xff\xff\xff\xff\xff\xff\xff\0\0\0\0\0\0)
windowState=@ByteArray(\0\0\0\xff\0\0\0\0\xfd\0\0\0\0\0\0\x4\xaa\0\0\x5\x9c\0\0\0\x4\0\0\0\x4\0\0\0\b\0\0\0\b\xfc\0\0\0\x1\0\0\0\0\0\0\0\x1\xff\xff\xff\xff\x3\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0)
headerState=@ByteArray(\0\0\0\xff\0\0\0\0\0\0\0\x1\0\0\0\x1\0\0\0\0\x1\0\0\0\0\0\0\0\0\0\0\0\x16\0\xe0?\0\0\0\t\0\0\0\x10\0\0\0\x64\0\0\0\xf\0\0\0\x64\0\0\0\xe\0\0\0\x64\0\0\0\r\0\0\0\x64\0\0\0\x15\0\0\0\x64\0\0\0\x14\0\0\0\x64\0\0\0\x13\0\0\0\x64\0\0\0\x12\0\0\0\x64\0\0\0\x11\0\0\0\x64\0\0\x4\xd3\0\0\0\x16\x1\x1\0\x1\0\0\0\0\0\0\0\0\0\0\0\0\x64\xff\xff\xff\xff\0\0\0\x81\0\0\0\0\0\0\0\x3\0\0\0#\0\0\0\x1\0\0\0\x2\0\0\x4\xb0\0\0\0\f\0\0\0\0\0\0\0\0\0\0\0\t\0\0\0\0)
[impl1%3CStrategy1%3E]
isChecked=true
isHidden=false
isExpanded=false
[General]
AutoAssign=true
Export.auto_tasks=TimingSimFileVlg, Bitgen, Jedecgen
PAR.auto_tasks=PARTrace, IOTiming
Map.auto_tasks=MapTrace, MapVerilogSimFile
[General]
COLUMN_POS_INFO_NAME_-1_0=Prioritize
COLUMN_POS_INFO_NAME_-1_1=PIO Register
[General]
pin_sort_type=0
pin_sort_ascending=true
sig_sort_type=0
sig_sort_ascending=true
active_Sheet=Port Assignments
[Port%20Assignments]
Name="80,0"
Group%20By="84,1"
Pin="50,2"
BANK="62,3"
BANK_VCC="90,4"
VREF="60,5"
IO_TYPE="80,6"
PULLMODE="92,7"
DRIVE="67,8"
SLEWRATE="92,9"
CLAMP="71,10"
OPENDRAIN="97,11"
DIFFRESISTOR="114,12"
DIFFDRIVE="92,13"
HYSTERESIS="101,14"
Outload%20%28pF%29="103,15"
MaxSkew="87,16"
Clock%20Load%20Only="121,17"
SwitchingID="100,18"
Ground%20plane%20PCB%20noise%20%28mV%29="196,19"
Power%20plane%20PCB%20noise%20%28mV%29="190,20"
SSO%20Allowance%28%25%29="138,21"
sort_columns="Name,Ascending"
[Pin%20Assignments]
Pin="90,0"
Pad%20Name="89,1"
Dual%20Function="261,2"
Polarity="77,3"
BANK="0,4"
BANK_VCC="90,5"
IO_TYPE="80,6"
Signal%20Name="102,7"
Signal%20Type="98,8"
sort_columns="Pin,Ascending"
[Clock%20Resource]
Clock%20Type="100,ELLIPSIS"
Clock%20Name="100,ELLIPSIS"
Selection="100,ELLIPSIS"
[Global%20Preferences]
Preference%20Name="231,ELLIPSIS"
Preference%20Value="236,ELLIPSIS"
[Cell%20Mapping]
Type="100,ELLIPSIS"
Name="100,ELLIPSIS"
Din\Dout="100,ELLIPSIS"
PIO%20Register="100,ELLIPSIS"
[Route%20Priority]
Type="100,ELLIPSIS"
Name="100,ELLIPSIS"
Prioritize="100,ELLIPSIS"
[Timing%20Preferences]
Preference%20Name="129,ELLIPSIS"
Preference%20Value="105,ELLIPSIS"
Preference%20Unit="98,ELLIPSIS"
[Group]
Group%20Type\Name="134,ELLIPSIS"
Value="39,ELLIPSIS"
[Misc%20Preferences]
Preference%20Name="117,ELLIPSIS"
Preference%20Value="105,ELLIPSIS"
<!DOCTYPE ispTLA>
<ispTLA>
<CreationDate>Wed Jan 2 12:18:39 2019</CreationDate>
<XCFFileName/>
<CableSetting>
<IsTRSTConnected val="false"/>
<TRSTSetting val="0"/>
<IsBSCANConnected val="false"/>
<BSCANSetting val="0"/>
<CableType val="USB2"/>
<PortAddress val="0"/>
<PortSetting val="0"/>
<TCKDelay val="1"/>
</CableSetting>
<DeviceCount>1</DeviceCount>
<Device>
<DeviceIndex>0</DeviceIndex>
<DeviceName>1. LCMXO3LF-6900C</DeviceName>
<DeviceID>0x612BD043</DeviceID>
<HasIspTRACY>true</HasIspTRACY>
<HasJTAG2WB>false</HasJTAG2WB>
<SERDES/>
<IRBypassLen>8</IRBypassLen>
<RVLFileName>RevealInserter.rvl</RVLFileName>
<RVSFileName>RevealInserter.rvs</RVSFileName>
<LACoreCount>1</LACoreCount>
<WinUI CoreIndex="0">
<TraceSigTreeData>
<TraceSignal IsHidden="false" Name="TU1" NodeType="0" PortIndex="56"/>
<TraceSignal IsHidden="false" Name="data_addr" NodeType="1" PortIndex="0">
<BusRadix Radix="3"/>
<IsExpanded Expand="false"/>
</TraceSignal>
<TraceSignal IsHidden="false" Name="data_addr:0" NodeType="2" PortIndex="0"/>
<TraceSignal IsHidden="false" Name="data_addr:1" NodeType="2" PortIndex="1"/>
<TraceSignal IsHidden="false" Name="data_addr:2" NodeType="2" PortIndex="2"/>
<TraceSignal IsHidden="false" Name="data_addr:3" NodeType="2" PortIndex="3"/>
<TraceSignal IsHidden="false" Name="data_addr:4" NodeType="2" PortIndex="4"/>
<TraceSignal IsHidden="false" Name="data_addr:5" NodeType="2" PortIndex="5"/>
<TraceSignal IsHidden="false" Name="data_addr:6" NodeType="2" PortIndex="6"/>
<TraceSignal IsHidden="false" Name="data_addr:7" NodeType="2" PortIndex="7"/>
<TraceSignal IsHidden="false" Name="data_addr:8" NodeType="2" PortIndex="8"/>
<TraceSignal IsHidden="false" Name="data_addr:9" NodeType="2" PortIndex="9"/>
<TraceSignal IsHidden="false" Name="data_addr:10" NodeType="2" PortIndex="10"/>
<TraceSignal IsHidden="false" Name="data_addr:11" NodeType="2" PortIndex="11"/>
<TraceSignal IsHidden="false" Name="data_addr:12" NodeType="2" PortIndex="12"/>
<TraceSignal IsHidden="false" Name="data_addr:13" NodeType="2" PortIndex="13"/>
<TraceSignal IsHidden="false" Name="data_addr:14" NodeType="2" PortIndex="14"/>
<TraceSignal IsHidden="false" Name="data_addr:15" NodeType="2" PortIndex="15"/>
<TraceSignal IsHidden="false" Name="leds" NodeType="1" PortIndex="16">
<BusRadix Radix="3"/>
<IsExpanded Expand="false"/>
</TraceSignal>
<TraceSignal IsHidden="false" Name="leds:0" NodeType="2" PortIndex="16"/>
<TraceSignal IsHidden="false" Name="leds:1" NodeType="2" PortIndex="17"/>
<TraceSignal IsHidden="false" Name="leds:2" NodeType="2" PortIndex="18"/>
<TraceSignal IsHidden="false" Name="leds:3" NodeType="2" PortIndex="19"/>
<TraceSignal IsHidden="false" Name="leds:4" NodeType="2" PortIndex="20"/>
<TraceSignal IsHidden="false" Name="leds:5" NodeType="2" PortIndex="21"/>
<TraceSignal IsHidden="false" Name="leds:6" NodeType="2" PortIndex="22"/>
<TraceSignal IsHidden="false" Name="leds:7" NodeType="2" PortIndex="23"/>
<TraceSignal IsHidden="false" Name="data_out" NodeType="1" PortIndex="24">
<BusRadix Radix="3"/>
<IsExpanded Expand="false"/>
</TraceSignal>
<TraceSignal IsHidden="false" Name="data_out:0" NodeType="2" PortIndex="24"/>
<TraceSignal IsHidden="false" Name="data_out:1" NodeType="2" PortIndex="25"/>
<TraceSignal IsHidden="false" Name="data_out:2" NodeType="2" PortIndex="26"/>
<TraceSignal IsHidden="false" Name="data_out:3" NodeType="2" PortIndex="27"/>
<TraceSignal IsHidden="false" Name="data_out:4" NodeType="2" PortIndex="28"/>
<TraceSignal IsHidden="false" Name="data_out:5" NodeType="2" PortIndex="29"/>
<TraceSignal IsHidden="false" Name="data_out:6" NodeType="2" PortIndex="30"/>
<TraceSignal IsHidden="false" Name="data_out:7" NodeType="2" PortIndex="31"/>
<TraceSignal IsHidden="false" Name="data_out:8" NodeType="2" PortIndex="32"/>
<TraceSignal IsHidden="false" Name="data_out:9" NodeType="2" PortIndex="33"/>
<TraceSignal IsHidden="false" Name="data_out:10" NodeType="2" PortIndex="34"/>
<TraceSignal IsHidden="false" Name="data_out:11" NodeType="2" PortIndex="35"/>
<TraceSignal IsHidden="false" Name="data_out:12" NodeType="2" PortIndex="36"/>
<TraceSignal IsHidden="false" Name="data_out:13" NodeType="2" PortIndex="37"/>
<TraceSignal IsHidden="false" Name="data_out:14" NodeType="2" PortIndex="38"/>
<TraceSignal IsHidden="false" Name="data_out:15" NodeType="2" PortIndex="39"/>
<TraceSignal IsHidden="false" Name="data_out:16" NodeType="2" PortIndex="40"/>
<TraceSignal IsHidden="false" Name="data_out:17" NodeType="2" PortIndex="41"/>
<TraceSignal IsHidden="false" Name="data_out:18" NodeType="2" PortIndex="42"/>
<TraceSignal IsHidden="false" Name="data_out:19" NodeType="2" PortIndex="43"/>
<TraceSignal IsHidden="false" Name="data_out:20" NodeType="2" PortIndex="44"/>
<TraceSignal IsHidden="false" Name="data_out:21" NodeType="2" PortIndex="45"/>
<TraceSignal IsHidden="false" Name="data_out:22" NodeType="2" PortIndex="46"/>
<TraceSignal IsHidden="false" Name="data_out:23" NodeType="2" PortIndex="47"/>
<TraceSignal IsHidden="false" Name="data_out:24" NodeType="2" PortIndex="48"/>
<TraceSignal IsHidden="false" Name="data_out:25" NodeType="2" PortIndex="49"/>
<TraceSignal IsHidden="false" Name="data_out:26" NodeType="2" PortIndex="50"/>
<TraceSignal IsHidden="false" Name="data_out:27" NodeType="2" PortIndex="51"/>
<TraceSignal IsHidden="false" Name="data_out:28" NodeType="2" PortIndex="52"/>
<TraceSignal IsHidden="false" Name="data_out:29" NodeType="2" PortIndex="53"/>
<TraceSignal IsHidden="false" Name="data_out:30" NodeType="2" PortIndex="54"/>
<TraceSignal IsHidden="false" Name="data_out:31" NodeType="2" PortIndex="55"/>
</TraceSigTreeData>
<TriggerUI UserSelect="0" PreSelectType="0" PreSelect="1" UserSelectPos="0"/>
<CoreRun Run="true"/>
<CoreWndUIData>
<ClockFrequency Unit="ns" Frequency="-1.0"/>
</CoreWndUIData>
</WinUI>
</Device>
</ispTLA>
This diff is collapsed.
This diff is collapsed.
<Project ModBy="Inserter" SigType="0" Name="C:/GitHub/VERILOG-RISC-V-LIGHT-CORE-IP-TST-LATTICE/RevealInserter.rvl" Date="2019-01-02">
<IP Version="1_6_042617"/>
<Design DesignEntry="Schematic/Verilog HDL" Synthesis="lse" DeviceFamily="MachXO3LF" DesignName="VERILOG_RISC_V_LIGHT_CORE_IP_TST_LATTICE"/>
<Core InsertDataset="0" Insert="1" Reveal_sig="205868108" Name="top_LA0" ID="0">
<Setting>
<Clock SampleClk="core_clk" SampleEnable="0" EnableClk="" EnableClk_Pri="0"/>
<TraceBuffer Implementation="0" BitTimeStamp="0" hasTimeStamp="0" IncTrigSig="1" BufferDepth="512"/>
<Capture Mode="1" MinSamplesPerTrig="8"/>
<Event CntEnable="0" MaxEventCnt="8"/>
<TrigOut Polarity="0" MinPulseWidth="0" TrigOutNetType="1" EnableTrigOut="0" TrigOutNet="reveal_debug_top_LA0_net"/>
<DistRAM Disable="0"/>
</Setting>
<Dataset Name="Base">
<Trace>
<Bus Name="data_addr">
<Sig Type="SIG" Name="data_addr:0"/>
<Sig Type="SIG" Name="data_addr:1"/>
<Sig Type="SIG" Name="data_addr:2"/>
<Sig Type="SIG" Name="data_addr:3"/>
<Sig Type="SIG" Name="data_addr:4"/>
<Sig Type="SIG" Name="data_addr:5"/>
<Sig Type="SIG" Name="data_addr:6"/>
<Sig Type="SIG" Name="data_addr:7"/>
<Sig Type="SIG" Name="data_addr:8"/>
<Sig Type="SIG" Name="data_addr:9"/>
<Sig Type="SIG" Name="data_addr:10"/>
<Sig Type="SIG" Name="data_addr:11"/>
<Sig Type="SIG" Name="data_addr:12"/>
<Sig Type="SIG" Name="data_addr:13"/>
<Sig Type="SIG" Name="data_addr:14"/>
<Sig Type="SIG" Name="data_addr:15"/>
</Bus>
<Bus Name="leds">
<Sig Type="SIG" Name="leds:0"/>
<Sig Type="SIG" Name="leds:1"/>
<Sig Type="SIG" Name="leds:2"/>
<Sig Type="SIG" Name="leds:3"/>
<Sig Type="SIG" Name="leds:4"/>
<Sig Type="SIG" Name="leds:5"/>
<Sig Type="SIG" Name="leds:6"/>
<Sig Type="SIG" Name="leds:7"/>
</Bus>
<Bus Name="data_out">
<Sig Type="SIG" Name="data_out:0"/>
<Sig Type="SIG" Name="data_out:1"/>
<Sig Type="SIG" Name="data_out:2"/>
<Sig Type="SIG" Name="data_out:3"/>
<Sig Type="SIG" Name="data_out:4"/>
<Sig Type="SIG" Name="data_out:5"/>
<Sig Type="SIG" Name="data_out:6"/>
<Sig Type="SIG" Name="data_out:7"/>
<Sig Type="SIG" Name="data_out:8"/>
<Sig Type="SIG" Name="data_out:9"/>
<Sig Type="SIG" Name="data_out:10"/>
<Sig Type="SIG" Name="data_out:11"/>
<Sig Type="SIG" Name="data_out:12"/>
<Sig Type="SIG" Name="data_out:13"/>
<Sig Type="SIG" Name="data_out:14"/>
<Sig Type="SIG" Name="data_out:15"/>
<Sig Type="SIG" Name="data_out:16"/>
<Sig Type="SIG" Name="data_out:17"/>
<Sig Type="SIG" Name="data_out:18"/>
<Sig Type="SIG" Name="data_out:19"/>
<Sig Type="SIG" Name="data_out:20"/>
<Sig Type="SIG" Name="data_out:21"/>
<Sig Type="SIG" Name="data_out:22"/>
<Sig Type="SIG" Name="data_out:23"/>
<Sig Type="SIG" Name="data_out:24"/>
<Sig Type="SIG" Name="data_out:25"/>
<Sig Type="SIG" Name="data_out:26"/>
<Sig Type="SIG" Name="data_out:27"/>
<Sig Type="SIG" Name="data_out:28"/>
<Sig Type="SIG" Name="data_out:29"/>
<Sig Type="SIG" Name="data_out:30"/>
<Sig Type="SIG" Name="data_out:31"/>
</Bus>
</Trace>
<Trigger>
<TU Serialbits="0" Type="0" ID="1" Sig="data_write_b,"/>
<TE MaxSequence="2" MaxEvnCnt="1" ID="1" Resource="0"/>
</Trigger>
</Dataset>
</Core>
</Project>
<Project ModBy="Analyzer" Name="C:/GitHub/VERILOG-RISC-V-LIGHT-CORE-IP-TST-LATTICE/RevealInserter.rvs" Date="2019-01-02">
<Core Name="top_LA0">
<Setting>
<Capture SamplesPerTrig="8" NumTrigsCap="64"/>
<Event EventCnt="0" CntEnableRun="0"/>
<TrigSetting PreTrgSamples="" AND_ALL="0" PostTrgSamples="" TURadix="0"/>
</Setting>
<Dataset Name="Base">
<Trace>
<Bus Name="data_addr" Radix="0">
<Sig Name="data_addr:0"/>
<Sig Name="data_addr:1"/>
<Sig Name="data_addr:2"/>
<Sig Name="data_addr:3"/>
<Sig Name="data_addr:4"/>
<Sig Name="data_addr:5"/>
<Sig Name="data_addr:6"/>
<Sig Name="data_addr:7"/>
<Sig Name="data_addr:8"/>
<Sig Name="data_addr:9"/>
<Sig Name="data_addr:10"/>
<Sig Name="data_addr:11"/>
<Sig Name="data_addr:12"/>
<Sig Name="data_addr:13"/>
<Sig Name="data_addr:14"/>
<Sig Name="data_addr:15"/>
</Bus>
<Bus Name="leds" Radix="0">
<Sig Name="leds:0"/>
<Sig Name="leds:1"/>
<Sig Name="leds:2"/>
<Sig Name="leds:3"/>
<Sig Name="leds:4"/>
<Sig Name="leds:5"/>
<Sig Name="leds:6"/>
<Sig Name="leds:7"/>
</Bus>
<Bus Name="data_out" Radix="0">
<Sig Name="data_out:0"/>
<Sig Name="data_out:1"/>
<Sig Name="data_out:2"/>
<Sig Name="data_out:3"/>
<Sig Name="data_out:4"/>
<Sig Name="data_out:5"/>
<Sig Name="data_out:6"/>
<Sig Name="data_out:7"/>
<Sig Name="data_out:8"/>
<Sig Name="data_out:9"/>
<Sig Name="data_out:10"/>
<Sig Name="data_out:11"/>
<Sig Name="data_out:12"/>
<Sig Name="data_out:13"/>
<Sig Name="data_out:14"/>
<Sig Name="data_out:15"/>
<Sig Name="data_out:16"/>
<Sig Name="data_out:17"/>
<Sig Name="data_out:18"/>
<Sig Name="data_out:19"/>
<Sig Name="data_out:20"/>
<Sig Name="data_out:21"/>
<Sig Name="data_out:22"/>
<Sig Name="data_out:23"/>
<Sig Name="data_out:24"/>
<Sig Name="data_out:25"/>
<Sig Name="data_out:26"/>
<Sig Name="data_out:27"/>
<Sig Name="data_out:28"/>
<Sig Name="data_out:29"/>
<Sig Name="data_out:30"/>
<Sig Name="data_out:31"/>
</Bus>
</Trace>
<Trigger>
<TU Operator="6" Name="TU1" ID="1" Value="1" Radix="0"/>
<TE Enable="1" Expression="TU1" Name="TE1" ID="1"/>
</Trigger>
</Dataset>
</Core>
</Project>
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[Project]
Current Flow=Generic
VCS=0
version=3
Current Config=compile
[Configurations]
compile=work
[Library]
Simulation=.\Simulation\Simulation.lib
[Settings]
AccessRead=1
AccessReadWrite=0
AccessACCB=0
AccessACCR=0
AccessReadWriteSLP=0
AccessReadTopLevel=0
DisableC=1
ENABLE_ADV_DATAFLOW=0
FLOW_TYPE=HDL
LANGUAGE=VHDL
REFRESH_FLOW=1
fileopenfolder=C:\GitHub\VERILOG-RISC-V-LIGHT-CORE-IP-TST-LATTICE
[LocalVerilogSets]
EnableSLP=1
EnableDebug=0
PriorityLibNames=pmi_work
LibNames=ovi_machxo3l
[LocalVhdlSets]
CompileWithDebug=0
[$LibMap$]
simulation=.
work=.
[LocalVerilogDirs]
Count=0
[DefineMacro]
Global=
[Files]
/..\..\..\VERILOG-RISC-V-LIGHT\VERILOG-RISC-V.srcs\sources_1\imports\io\pio_s.v=-1
/..\..\..\VERILOG-RISC-V-LIGHT\VERILOG-RISC-V.srcs\sources_1\imports\io\rtc_s.v=-1
/..\..\..\VERILOG-RISC-V-LIGHT\VERILOG-RISC-V.srcs\sources_1\new\reg.v=-1
/..\..\..\VERILOG-RISC-V-LIGHT\VERILOG-RISC-V.srcs\sources_1\new\risc-v-alu-l.v=-1
/..\..\..\VERILOG-RISC-V-LIGHT\VERILOG-RISC-V.srcs\sources_1\new\risc-v-lite.v=-1
/..\..\..\VERILOG-RISC-V-LIGHT\VERILOG-RISC-V.srcs\sources_1\new\memory.v=-1
/..\..\rom.v=-1
/..\..\top.v=-1
/..\..\impl1\source\top_sim.v=-1
/..\..\..\VERILOG-RISC-V-LIGHT\VERILOG-RISC-V.srcs\sources_1\new\risc-v-l-h.v=-1
/..\..\..\VERILOG-RISC-V-LIGHT\VERILOG-RISC-V.srcs\sources_1\imports\io\io_s_h.v=-1
/..\..\core1ROM.mem=-1
[Files.Data]
.\..\..\VERILOG-RISC-V-LIGHT\VERILOG-RISC-V.srcs\sources_1\imports\io\pio_s.v=Verilog Source Code
.\..\..\VERILOG-RISC-V-LIGHT\VERILOG-RISC-V.srcs\sources_1\imports\io\rtc_s.v=Verilog Source Code
.\..\..\VERILOG-RISC-V-LIGHT\VERILOG-RISC-V.srcs\sources_1\new\reg.v=Verilog Source Code
.\..\..\VERILOG-RISC-V-LIGHT\VERILOG-RISC-V.srcs\sources_1\new\risc-v-alu-l.v=Verilog Source Code
.\..\..\VERILOG-RISC-V-LIGHT\VERILOG-RISC-V.srcs\sources_1\new\risc-v-lite.v=Verilog Source Code
.\..\..\VERILOG-RISC-V-LIGHT\VERILOG-RISC-V.srcs\sources_1\new\memory.v=Verilog Source Code
.\..\rom.v=Verilog Source Code
.\..\top.v=Verilog Source Code
.\..\impl1\source\top_sim.v=Verilog Source Code
.\..\..\VERILOG-RISC-V-LIGHT\VERILOG-RISC-V.srcs\sources_1\new\risc-v-l-h.v=Verilog Source Code
.\..\..\VERILOG-RISC-V-LIGHT\VERILOG-RISC-V.srcs\sources_1\imports\io\io_s_h.v=Verilog Source Code
.\..\core1ROM.mem=Memory File
[SpecTracer]
WindowVisible=0
[HierarchyViewer]
HierarchyInformation=
ShowHide=ShowTopLevel
Selected=
setenv SIM_WORKING_FOLDER .
set newDesign 0
if {![file exists "C:/GitHub/VERILOG-RISC-V-LIGHT-CORE-IP-TST-LATTICE/Simulation/Simulation.adf"]} {
design create Simulation "C:/GitHub/VERILOG-RISC-V-LIGHT-CORE-IP-TST-LATTICE"
set newDesign 1
}
design open "C:/GitHub/VERILOG-RISC-V-LIGHT-CORE-IP-TST-LATTICE/Simulation"
cd "C:/GitHub/VERILOG-RISC-V-LIGHT-CORE-IP-TST-LATTICE"
designverincludedir -clear
designverlibrarysim -PL -clear
designverlibrarysim -L -clear
designverlibrarysim -PL pmi_work
designverlibrarysim ovi_machxo3l
designverdefinemacro -clear
if {$newDesign == 0} {
removefile -Y -D *
}
addfile "C:/GitHub/VERILOG-RISC-V-LIGHT/VERILOG-RISC-V.srcs/sources_1/imports/io/pio_s.v"
addfile "C:/GitHub/VERILOG-RISC-V-LIGHT/VERILOG-RISC-V.srcs/sources_1/imports/io/rtc_s.v"
addfile "C:/GitHub/VERILOG-RISC-V-LIGHT/VERILOG-RISC-V.srcs/sources_1/new/reg.v"
addfile "C:/GitHub/VERILOG-RISC-V-LIGHT/VERILOG-RISC-V.srcs/sources_1/new/risc-v-alu-l.v"
addfile "C:/GitHub/VERILOG-RISC-V-LIGHT/VERILOG-RISC-V.srcs/sources_1/new/risc-v-lite.v"
addfile "C:/GitHub/VERILOG-RISC-V-LIGHT/VERILOG-RISC-V.srcs/sources_1/new/memory.v"
addfile "C:/GitHub/VERILOG-RISC-V-LIGHT-CORE-IP-TST-LATTICE/rom.v"
addfile "C:/GitHub/VERILOG-RISC-V-LIGHT-CORE-IP-TST-LATTICE/top.v"
addfile "C:/GitHub/VERILOG-RISC-V-LIGHT-CORE-IP-TST-LATTICE/impl1/source/top_sim.v"
addfile "C:/GitHub/VERILOG-RISC-V-LIGHT/VERILOG-RISC-V.srcs/sources_1/new/risc-v-l-h.v"
addfile "C:/GitHub/VERILOG-RISC-V-LIGHT/VERILOG-RISC-V.srcs/sources_1/imports/io/io_s_h.v"
vlib "C:/GitHub/VERILOG-RISC-V-LIGHT-CORE-IP-TST-LATTICE/Simulation/work"
set worklib work
adel -all
vlog -dbg -work work "C:/GitHub/VERILOG-RISC-V-LIGHT/VERILOG-RISC-V.srcs/sources_1/imports/io/pio_s.v"
vlog -dbg -work work "C:/GitHub/VERILOG-RISC-V-LIGHT/VERILOG-RISC-V.srcs/sources_1/imports/io/rtc_s.v"
vlog -dbg -work work "C:/GitHub/VERILOG-RISC-V-LIGHT/VERILOG-RISC-V.srcs/sources_1/new/reg.v"
vlog -dbg -work work "C:/GitHub/VERILOG-RISC-V-LIGHT/VERILOG-RISC-V.srcs/sources_1/new/risc-v-alu-l.v"
vlog -dbg -work work "C:/GitHub/VERILOG-RISC-V-LIGHT/VERILOG-RISC-V.srcs/sources_1/new/risc-v-lite.v"
vlog -dbg -work work "C:/GitHub/VERILOG-RISC-V-LIGHT/VERILOG-RISC-V.srcs/sources_1/new/memory.v"
vlog -dbg -work work "C:/GitHub/VERILOG-RISC-V-LIGHT-CORE-IP-TST-LATTICE/rom.v"
vlog -dbg -work work "C:/GitHub/VERILOG-RISC-V-LIGHT-CORE-IP-TST-LATTICE/top.v"
vlog -dbg -work work "C:/GitHub/VERILOG-RISC-V-LIGHT-CORE-IP-TST-LATTICE/impl1/source/top_sim.v"
vlog -dbg -work work "C:/GitHub/VERILOG-RISC-V-LIGHT/VERILOG-RISC-V.srcs/sources_1/new/risc-v-l-h.v"
vlog -dbg -work work "C:/GitHub/VERILOG-RISC-V-LIGHT/VERILOG-RISC-V.srcs/sources_1/imports/io/io_s_h.v"
module top_sim
vsim +access +r top_sim -PL pmi_work -L ovi_machxo3l
add wave *
run 1000ns
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pio_s,/,C:/GitHub/VERILOG-RISC-V-LIGHT/VERILOG-RISC-V.srcs/sources_1/imports/io/pio_s.v
rtc_s,/,C:/GitHub/VERILOG-RISC-V-LIGHT/VERILOG-RISC-V.srcs/sources_1/imports/io/rtc_s.v
top_sim,/,C:/GitHub/VERILOG-RISC-V-LIGHT-CORE-IP-TST-LATTICE/impl1/source/top_sim.v
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