Commit 1ecd17c1 authored by Iulian Gheorghiu's avatar Iulian Gheorghiu

Update project to the latest changes.

parent 23106dea
......@@ -9,6 +9,6 @@ showLPF=true
showREGIONs=true
showUGROUPs=true
showPARITIONs=true
showLogicalConnections=false
showLogicalConnections=true
dontShowBBoxOverlapWarning=false
sceneInViewRect="@Variant(\0\0\0\x14\xc1\x3\x15\x96\xda\xa4=K\xc0\xec\xf2\v0\xb8\x8d\xdd\x41\x1dr]\xc3\xeJ\bA\v6\xbf\x65\xbe\xec\x8d)"
sceneInViewRect=@Variant(\0\0\0\x14\xc0\x94\x8cg\x83\xc8\x42\xe2\xc0\xe6\x37\xcf\xec\xe3\xbb\x85\x41\x5\x3\x95\xdc*\xff\x9a\x41\a\xd2\xc8\x3/`\xbe)
......@@ -3,7 +3,6 @@
<name>TestRiscVLattice</name>
<comment></comment>
<projects>
<project>TestRiscVXilinx</project>
</projects>
<buildSpec>
<buildCommand>
......
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
......@@ -4,16 +4,15 @@ ENTRY(_entry)
MEMORY
{
envm (rx) : ORIGIN = 0x8000, LENGTH = 4k
ram (rwx) : ORIGIN = 0x4000, LENGTH = 8k
ROM (rx) : ORIGIN = 0x8000, LENGTH = 4k
RAM (rwx) : ORIGIN = 0x4000, LENGTH = 8k
}
RAM_START_ADDRESS = 0x4000; /* Must be the same value MEMORY region ram ORIGIN above. */
RAM_SIZE = 8k; /* Must be the same value MEMORY region ram LENGTH above. */
HEAP_SIZE = 2k; /* needs to be calculated for your application */
SDATA_SIZE = 2K; /* needs to be calculated for your application */
STACK_SIZE = 1k; /* needs to be calculated for your application */
RAM_START_ADDRESS = ORIGIN(RAM); /* Must be the same value MEMORY region RAM ORIGIN above. */
RAM_SIZE = LENGTH(RAM); /* Must be the same value MEMORY region RAM LENGTH above. */
__stack = ORIGIN(RAM) + LENGTH(RAM);
__stack_size = DEFINED(__stack_size) ? __stack_size : 2K;
SECTIONS
{
......@@ -57,73 +56,116 @@ SECTIONS
PROVIDE_HIDDEN (__fini_array_end = .);
. = ALIGN(0x10);
} >envm
} >ROM
/* short/global data section */
.sdata : ALIGN(0x10)
{
__sdata_load = LOADADDR(.sdata);
__sdata_start = .;
PROVIDE( __global_pointer$ = . + SDATA_SIZE);
*(.srodata.cst16) *(.srodata.cst8) *(.srodata.cst4) *(.srodata.cst2)
*(.srodata*)
*(.sdata .sdata.* .gnu.linkonce.s.*)
. = ALIGN(0x10);
__sdata_end = .;
} >ram AT>envm
/* data section */
.data : ALIGN(0x10)
{
__data_load = LOADADDR(.data);
__data_start = .;
*(.got.plt) *(.got)
*(.shdata)
*(.data .data.* .gnu.linkonce.d.*)
. = ALIGN(0x10);
__data_end = .;
__edata = __data_end;
} >ram AT>envm
_edata = .;
_sdata_size = SDATA_SIZE;
/* sbss section */
.sbss : ALIGN(0x10)
{
__sbss_start = .;
*(.sbss .sbss.* .gnu.linkonce.sb.*)
*(.scommon)
. = ALIGN(0x10);
__sbss_end = .;
} > ram
/* sbss section */
.bss : ALIGN(0x10)
{
__bss_start = .;
*(.shbss)
*(.bss .bss.* .gnu.linkonce.b.*)
*(COMMON)
. = ALIGN(0x10);
__bss_end = .;
} > ram
.data : ALIGN(4)
{
FILL(0xFF)
__data_start__ = . ; /* Standard newlib definition. */
__data_begin__ = . ; /* µOS++ specific */
*(.data_begin .data_begin.*) /* µOS++ __data_begin_guard */
/* End of uninitialized data segment */
_end = .;
.heap : ALIGN(0x10)
{
__heap_start = .;
. += HEAP_SIZE;
__heap_end = .;
. = ALIGN(0x10);
_heap_end = __heap_end;
} > ram
.stack : ALIGN(0x10)
*(.data .data.*)
*(.gnu.linkonce.d.*)
. = ALIGN(8);
/*
* RISC-V specific; the compiler optimises memory accesses
* in the +/- 2K range around __global_pointer$ to GP relative.
* For this to work, GP must be loaded during startup with the
* address of __global_pointer$.
* This optimisation favours a 4K range. Newlib places
* several impure and malloc pointers in the .sdata section.
*/
PROVIDE( __global_pointer$ = . + (4K / 2) );
*(.sdata .sdata.*)
*(.gnu.linkonce.s.*)
/* RISC-V specific; not sure if needed. */
. = ALIGN(8);
*(.srodata.cst16)
*(.srodata.cst8)
*(.srodata.cst4)
*(.srodata.cst2)
*(.srodata .srodata.*)
*(.data_end .data_end.*) /* µOS++ __data_end_guard; must be last */
. = ALIGN(4);
__data_end__ = . ; /* Standard newlib definition. */
} >RAM AT>ROM
/*
* This address is used by the µOS++ startup code to
* initialise the .data section.
*/
__data_load_addr__ = LOADADDR(.data);
. = ALIGN(4);
PROVIDE( __edata = . );
PROVIDE( _edata = . );
PROVIDE( edata = . );
/* The primary uninitialised data section. */
.bss (NOLOAD) : ALIGN(4)
{
__bss_start = .; /* Standard newlib definition. */
__bss_start__ = .; /* Standard newlib definition. */
__bss_begin__ = .; /* µOS++ specific */
*(.bss_begin .bss_begin.*) /* µOS++ __bss_begin_guard */
*(.sbss .sbss.*)
*(.gnu.linkonce.sb.*)
*(.bss .bss.*)
*(.gnu.linkonce.b.*)
*(COMMON)
*(.bss_end .bss_end.*) /* µOS++ __bss_end_guard; must be last */
. = ALIGN(4);
__bss_end__ = .; /* Standard newlib definition. */
__bss_end = .; /* Standard newlib definition. */
} >RAM AT>RAM
/*
* Similar to .bss, but not initialised to zero. µOS++ extension.
*/
.noinit (NOLOAD) : ALIGN(4)
{
__noinit_begin__ = .; /* µOS++ extension. */
*(.noinit .noinit.*)
. = ALIGN(4) ;
__noinit_end__ = .; /* µOS++ extension. */
} >RAM AT>RAM
/* _sbrk() expects at least word alignment. */
. = ALIGN(8);
PROVIDE( __end = . );
PROVIDE( _end = . );
PROVIDE( end = . );
PROVIDE( __heap_begin__ = . ); /* µOS++ extension. */
.stack __stack - __stack_size :
{
PROVIDE( _heap_end = . ); /* Standard newlib definition. */
PROVIDE( __heap_end__ = . ); /* µOS++ extension. */
. += __stack_size;
} >RAM AT>RAM
/* Remove information from the compiler libraries */
/DISCARD/ :
{
__stack_bottom = .;
. += STACK_SIZE;
__stack_top = .;
} > ram
libc.a ( * )
libm.a ( * )
libgcc.a ( * )
}
}
\ No newline at end of file
......@@ -5,7 +5,7 @@
.globl _entry
_entry:
xor tp, tp, tp
/* xor tp, tp, tp
xor ra, ra, ra
xor t1, t1, t1
xor t2, t2, t2
......@@ -33,11 +33,21 @@ _entry:
xor t3, t3, t3
xor t4, t4, t4
xor t5, t5, t5
xor t6, t6, t6
la gp, __sdata_start
la t0, _sdata_size
add gp,gp,t0
la sp, __stack_top - 4
xor t6, t6, t6*/
.option push
// Ensure the instruction is not optimized, since gp is not yet set.
.option norelax
// __global_pointer$ is a magic symbol, known by the linker.
// Unless instructed not to do so, the linker optimizes
// accesses +/- 2KB around this to gp-relative.
la gp, __global_pointer$
.option pop
// The linker script usually defines the stack at the end of RAM.
la sp, __stack
// Proceed with the standard standard _begin() routine.
j _begin
......
......@@ -17,22 +17,14 @@
extern "C" {
#endif
extern uint32_t __sdata_load;
extern uint32_t __sdata_start;
extern uint32_t __sdata_end;
extern uint32_t __data_load;
extern uint32_t __data_start;
extern uint32_t __data_end;
extern uint32_t __data_load_addr__;
extern uint32_t __data_start__;
extern uint32_t __data_end__;
extern uint32_t __sbss_start;
extern uint32_t __sbss_end;
extern uint32_t __bss_start;
extern uint32_t __bss_end;
extern uint32_t __heap_start;
extern uint32_t __heap_end;
static void copy_section(uint32_t * p_load, uint32_t * p_vma, uint32_t * p_vma_end)
{
......@@ -57,21 +49,11 @@ static void zero_section(uint32_t * start, uint32_t * end)
void _begin(void)
{
copy_section(&__sdata_load, &__sdata_start, &__sdata_end);
copy_section(&__data_load, &__data_start, &__data_end);
zero_section(&__sbss_start, &__sbss_end);
copy_section(&__data_load_addr__, &__data_start__, &__data_end__);
zero_section(&__bss_start, &__bss_end);
zero_section(&__heap_start, &__heap_end);
asm volatile ("j _start");
}
/* Function called after main() finishes */
/*void
_fini()
{
}*/
#ifdef __cplusplus
}
#endif
......@@ -10,7 +10,7 @@
//using namespace std;
#include "riscv_hal.h"
#define CPU_FREQ (44330000)
#define CPU_FREQ (33250000)
//#define delay_cycles 250
#define delay_cycles (CPU_FREQ / 50)
#define RTC_PERIOD (CPU_FREQ / 1000)
......
......@@ -62,7 +62,7 @@ int (* const g_pfnVectors[])(unsigned int) =
ISR(IRQHandler)
{
ISR_PROLOGUE();
asm volatile
/*asm volatile
(
"xor t0, t0, t0" "\n\t"
"xor t1, t1, t1" "\n\t"
......@@ -92,7 +92,7 @@ ISR(IRQHandler)
"xor t4, t4, t4" "\n\t"
"xor t5, t5, t5" "\n\t"
"xor t6, t6, t6" "\n\t"
);
);*/
int interrupt_nr;
__asm__ __volatile__ (
"lw %0, 1*4(sp)"
......
......@@ -15,37 +15,40 @@
<Source name="sram.ipx" type="IPX_Module" type_short="IPX">
<Options/>
</Source>
<Source name="../VERILOG-IP/CORE/32BIT/RISC-V/memory.v" type="Verilog" type_short="Verilog">
<Source name="../VERILOG-IP/CORE/32BIT/RISC-V-LIGHT/memory.v" type="Verilog" type_short="Verilog">
<Options/>
</Source>
<Source name="../VERILOG-IP/CORE/32BIT/RISC-V/reg.v" type="Verilog" type_short="Verilog">
<Source name="../VERILOG-IP/CORE/32BIT/RISC-V-LIGHT/reg.v" type="Verilog" type_short="Verilog">
<Options/>
</Source>
<Source name="../VERILOG-IP/CORE/32BIT/RISC-V/risc-v-alu-l.v" type="Verilog" type_short="Verilog">
<Source name="../VERILOG-IP/CORE/32BIT/RISC-V-LIGHT/risc-v-alu-l.v" type="Verilog" type_short="Verilog">
<Options/>
</Source>
<Source name="../VERILOG-IP/CORE/32BIT/RISC-V/risc-v-l-h.v" type="Verilog" type_short="Verilog">
<Source name="../VERILOG-IP/CORE/32BIT/RISC-V-LIGHT/risc-v-l-h.v" type="Verilog" type_short="Verilog">
<Options/>
</Source>
<Source name="../VERILOG-IP/CORE/32BIT/RISC-V/risc-v-lite.v" type="Verilog" type_short="Verilog">
<Source name="../VERILOG-IP/CORE/32BIT/RISC-V-LIGHT/risc-v-lite.v" type="Verilog" type_short="Verilog">
<Options/>
</Source>
<Source name="../VERILOG-IP/CORE/32BIT/RISC-V/IO/io_s_h.v" type="Verilog" type_short="Verilog">
<Source name="../VERILOG-IP/CORE/32BIT/RISC-V-LIGHT/IO/io_s_h.v" type="Verilog" type_short="Verilog">
<Options/>
</Source>
<Source name="../VERILOG-IP/CORE/32BIT/RISC-V/IO/pio_s.v" type="Verilog" type_short="Verilog">
<Source name="../VERILOG-IP/CORE/32BIT/RISC-V-LIGHT/IO/pio_l.v" type="Verilog" type_short="Verilog">
<Options/>
</Source>
<Source name="../VERILOG-IP/CORE/32BIT/RISC-V/IO/rtc_s.v" type="Verilog" type_short="Verilog">
<Source name="../VERILOG-IP/CORE/32BIT/RISC-V-LIGHT/IO/pio_s.v" type="Verilog" type_short="Verilog">
<Options/>
</Source>
<Source name="../VERILOG-IP/CORE/32BIT/RISC-V/IO/spi_s.v" type="Verilog" type_short="Verilog">
<Source name="../VERILOG-IP/CORE/32BIT/RISC-V-LIGHT/IO/rtc_s.v" type="Verilog" type_short="Verilog">
<Options/>
</Source>
<Source name="../VERILOG-IP/CORE/32BIT/RISC-V/IO/twi_s.v" type="Verilog" type_short="Verilog">
<Source name="../VERILOG-IP/CORE/32BIT/RISC-V-LIGHT/IO/spi_s.v" type="Verilog" type_short="Verilog">
<Options/>
</Source>
<Source name="../VERILOG-IP/CORE/32BIT/RISC-V/IO/uart_s.v" type="Verilog" type_short="Verilog">
<Source name="../VERILOG-IP/CORE/32BIT/RISC-V-LIGHT/IO/twi_s.v" type="Verilog" type_short="Verilog">
<Options/>
</Source>
<Source name="../VERILOG-IP/CORE/32BIT/RISC-V-LIGHT/IO/uart_s.v" type="Verilog" type_short="Verilog">
<Options/>
</Source>
<Source name="core1ROM.mem" type="Unknown Type" type_short="Unknown">
......
00C0006F
5880006F
4FC0006F
00008067
00424233
0010C0B3
00634333
0073C3B3
00844433
0094C4B3
00A54533
00B5C5B3
00C64633
00D6C6B3
00E74733
00F7C7B3
01084833
0118C8B3
01294933
0139C9B3
00A54533
014A4A33
015ACAB3
016B4B33
017BCBB3
018C4C33
019CCCB3
01AD4D33
01BDCDB3
01CE4E33
01DECEB3
01EF4F33
01FFCFB3
FFFFC197
F8018193
FFFF8297
77828293
005181B3
53C18113
1500006F
00000000
FFFFC197
76018193
87018513
94018613
FFFFD197
85418193
FFFFE117
FEC10113
1680006F
FFFFD197
84018193
FFFFC517
04050513
8C018613
40A60633
00000593
7D4000EF
754000EF
00000517
6C850513
668000EF
72C000EF
64850513
5E8000EF
6AC000EF
00012503
00410593
00000613
484000EF
6640006F
474000EF
5E40006F
00008067
87018513
87018793
FFFFC517
00050513
FFFFC797
FF878793
00A78A63
FFFF8317
F1030313
F8430313
00030463
00030067
00008067
87018513
87018593
FFFFC517
FD850513
FFFFC597
FD058593
40A585B3
4025D593
01F5D793
......@@ -72,42 +45,44 @@ F1030313
4015D593
00058A63
FFFF8317
EDC30313
F4830313
00030463
00030067
00008067
8701C783
04079063
FFFFC797
F9C7C783
04079263
FF010113
00112623
F9DFF0EF
F89FF0EF
FFFF8797
EB478793
F1C78793
00078A63
00001517
A6850513
9D050513
FFFF8097
EA0080E7
F08080E7
00C12083
00100793
86F18823
FFFFC717
F6F70023
01010113
00008067
00008067
FFFF8797
E8078793
EE478793
02078663
FF010113
89018593
81C18593
00001517
A2C50513
99050513
00112623
FFFF8097
E60080E7
EC4080E7
00C12083
01010113
F55FF06F
F51FF06F
F45FF06F
F41FF06F
0140006F
00052783
00F5A023
......@@ -122,34 +97,24 @@ FEB56CE3
00008067
FF010113
00112623
81018613
80818613
000045B7
00058593
00009537
BD050513
AD050513
FB5FF0EF
87018613
81018593
00009537
BE050513
FA1FF0EF
89018593
87018513
FB1FF0EF
94018593
89018513
FA5FF0EF
14018593
94018513
F99FF0EF
E61FF06F
8C018593
00004537
06850513
FC1FF0EF
E6DFF06F
00C12083
01010113
00008067
00000793
86A1AC23
86F1AE23
87818793
80A1A823
80F1AA23
81018793
0007A603
0047A683
FFF60713
......@@ -344,12 +309,12 @@ D21FF0EF
FF010113
00112623
00812423
000D8437
74840513
000A2437
5A840513
D25FF0EF
74840513
5A840513
E0DFF0EF
74840513
5A840513
EF5FF0EF
FE5FF06F
0000006F
......@@ -387,38 +352,10 @@ F7C10113
09F12023
00012223
00012023
0052C2B3
00634333
0073C3B3
00844433
0094C4B3
00A54533
00B5C5B3
00C64633
00D6C6B3
00E74733
00F7C7B3
01084833
0118C8B3
01294933
0139C9B3
00A54533
014A4A33
015ACAB3
016B4B33
017BCBB3
018C4C33
019CCCB3
01AD4D33
01BDCDB3
01CE4E33
01DECEB3
01EF4F33
01FFCFB3
00412503
00251713
000097B7
B8078793
A8078793
00E787B3
0007A783
000780E7
......@@ -472,7 +409,7 @@ FF010113
00000593
2AC000EF
FFFFC797
89C78793
9F878793
0007A503
02852783
00078463
......@@ -481,10 +418,10 @@ FFFFC797
FA9FF0EF
FF010113
00000797
44078793
43C78793
00812423
00000417
43040413
42C40413
40878433
00912223
01212023
......@@ -498,7 +435,7 @@ FF010113
00412483
00012903
01010113
911FF06F
991FF06F
FFC00593
00048513
374000EF
......@@ -511,9 +448,9 @@ FF010113
00812423
00912223
00000417
3C040413
3BC40413
00000497
3B848493
3B448493
408484B3
01212023
00112623
......@@ -521,11 +458,11 @@ FF010113
00000913
04991063
00000417
39840413
39440413
00000497
39448493
39048493
408484B3
8A5FF0EF
925FF0EF
4024D493
00000913
02991863
......@@ -600,18 +537,18 @@ FF078793
00F60633
F6C378E3
F3DFF06F
88018793
81818793
0007A783
00050E13
02079463
8A818713
88E1A023
83418713
80E1AC23
FFFF7517
68050513
77C50513
00070793
00050863
00052783
92F1A823
8AF1AE23
00070793
0047A703
01F00813
......@@ -656,7 +593,7 @@ FD010113
01A12023
00050C13
00058B13
88018B93
81818B93
00100C93
000BA403