Commit a9db3550 authored by Iulian Gheorghiu's avatar Iulian Gheorghiu

From now on on peripheral displays the drivers will no longer do automatically…

From now on on peripheral displays the drivers will no longer do automatically refresh of the display, this will increase the speed of of painting, but the application will need to update the display after the vbuffer is modified.
parent 22d3470c
...@@ -378,6 +378,7 @@ void main_app(void) ...@@ -378,6 +378,7 @@ void main_app(void)
#endif #endif
dev.SCREEN[0]->drawLine(90, 16, 110, 25, 1, Color::White);//Complex inclined line. dev.SCREEN[0]->drawLine(90, 16, 110, 25, 1, Color::White);//Complex inclined line.
dev.SCREEN[0]->drawLine(98, 16, 118, 25, 3, Color::White);//Complex inclined line. dev.SCREEN[0]->drawLine(98, 16, 118, 25, 3, Color::White);//Complex inclined line.
dev.SCREEN[0]->refresh();
#endif #endif
#ifdef _USE_SSD1331 #ifdef _USE_SSD1331
if(ssd1331_0)/* This display driver is used like an external device (non registered display driver), you can declare more displays in this form, even multiplexed on same SPI interface. */ if(ssd1331_0)/* This display driver is used like an external device (non registered display driver), you can declare more displays in this form, even multiplexed on same SPI interface. */
...@@ -397,6 +398,7 @@ void main_app(void) ...@@ -397,6 +398,7 @@ void main_app(void)
#endif #endif
ssd1331_0->drawLine(90, 16, 110, 25, 1, Color::YellowGreen);//Complex inclined line. ssd1331_0->drawLine(90, 16, 110, 25, 1, Color::YellowGreen);//Complex inclined line.
ssd1331_0->drawLine(98, 16, 118, 25, 3, Color::Red);//Complex inclined line. ssd1331_0->drawLine(98, 16, 118, 25, 3, Color::Red);//Complex inclined line.
ssd1331_0->refresh();
} }
#endif #endif
#ifdef _USE_SSD1306 #ifdef _USE_SSD1306
...@@ -417,6 +419,7 @@ void main_app(void) ...@@ -417,6 +419,7 @@ void main_app(void)
#endif #endif
ssd1306_0->drawLine(90, 16, 110, 25, 1, Color::White);//Complex inclined line. ssd1306_0->drawLine(90, 16, 110, 25, 1, Color::White);//Complex inclined line.
ssd1306_0->drawLine(98, 16, 118, 25, 3, Color::White);//Complex inclined line. ssd1306_0->drawLine(98, 16, 118, 25, 3, Color::White);//Complex inclined line.
ssd1306_0->refresh();
} }
#endif #endif
...@@ -544,9 +547,11 @@ _continue: ...@@ -544,9 +547,11 @@ _continue:
GI::IO::write((string)"led-0", false); GI::IO::write((string)"led-0", false);
#ifdef _USE_SSD1331 #ifdef _USE_SSD1331
ssd1331_0->drawRectangle(1, 32, 5, 5, true, Color::Black); ssd1331_0->drawRectangle(1, 32, 5, 5, true, Color::Black);
ssd1331_0->refresh();
#endif #endif
#ifdef _USE_SSD1306 #ifdef _USE_SSD1306
ssd1306_0->drawRectangle(96, 24, 5, 5, true, Color::Black); ssd1306_0->drawRectangle(96, 24, 5, 5, true, Color::Black);
ssd1306_0->refresh();
#endif #endif
} }
else else
...@@ -555,9 +560,11 @@ _continue: ...@@ -555,9 +560,11 @@ _continue:
GI::IO::write((string)"led-0", true); GI::IO::write((string)"led-0", true);
#ifdef _USE_SSD1331 #ifdef _USE_SSD1331
ssd1331_0->drawRectangle(1, 32, 5, 5, true, Color::Red); ssd1331_0->drawRectangle(1, 32, 5, 5, true, Color::Red);
ssd1331_0->refresh();
#endif #endif
#ifdef _USE_SSD1306 #ifdef _USE_SSD1306
ssd1306_0->drawRectangle(96, 24, 5, 5, true, Color::White); ssd1306_0->drawRectangle(96, 24, 5, 5, true, Color::White);
ssd1306_0->refresh();
#endif #endif
} }
} }
......
This source diff could not be displayed because it is too large. You can view the blob instead.
...@@ -234,7 +234,7 @@ SysErr GI::Display::Display::drawCircle(signed int x, signed int y, signed int _ ...@@ -234,7 +234,7 @@ SysErr GI::Display::Display::drawCircle(signed int x, signed int y, signed int _
else else
P += 5 + 2 * (a++ - b--); P += 5 + 2 * (a++ - b--);
} while (a <= b); } while (a <= b);
refresh(); //refresh();
return SYS_ERR_OK; return SYS_ERR_OK;
} }
//####################################################################################### //#######################################################################################
...@@ -414,7 +414,7 @@ SysErr GI::Display::Display::drawLine(signed int X1, signed int Y1, signed int X ...@@ -414,7 +414,7 @@ SysErr GI::Display::Display::drawLine(signed int X1, signed int Y1, signed int X
} }
} }
} }
refresh(); //refresh();
return SYS_ERR_OK; return SYS_ERR_OK;
} }
...@@ -499,7 +499,7 @@ SysErr GI::Display::Display::drawElipse(signed int xc,signed int yc,signed int _ ...@@ -499,7 +499,7 @@ SysErr GI::Display::Display::drawElipse(signed int xc,signed int yc,signed int _
} }
elipseplot(this, xc, yc, x, y, Fill, color); elipseplot(this, xc, yc, x, y, Fill, color);
} }
refresh(); //refresh();
return SYS_ERR_OK; return SYS_ERR_OK;
} }
...@@ -595,7 +595,7 @@ SysErr GI::Display::Display::drawTriangle(signed int Ax,signed int Ay,signed i ...@@ -595,7 +595,7 @@ SysErr GI::Display::Display::drawTriangle(signed int Ax,signed int Ay,signed i
Ex += dx2; Ex += dx2;
} }
} }
refresh(); //refresh();
return SYS_ERR_OK; return SYS_ERR_OK;
} }
//####################################################################################### //#######################################################################################
...@@ -616,15 +616,20 @@ int GI::Display::Display::drawString(char *string, signed int X, signed int Y, t ...@@ -616,15 +616,20 @@ int GI::Display::Display::drawString(char *string, signed int X, signed int Y, t
tRectangle int_box; tRectangle int_box;
if(box) if(box)
{ {
int_box.sXMin = box->sXMin;
int_box.sXMax = box->sXMax;
int_box.sYMin = box->sYMin;
int_box.sYMax = box->sYMax;
}
else
{
int_box.sXMin = 0; int_box.sXMin = 0;
int_box.sXMax = LcdTimings->X; int_box.sXMax = LcdTimings->X;
int_box.sYMin = 0; int_box.sYMin = 0;
int_box.sYMax = LcdTimings->Y; int_box.sYMax = LcdTimings->Y;
box = &int_box;
} }
char *pcString = string; char *pcString = string;
bool WordWrap = wordWrap; bool WordWrap = wordWrap;
int lLength = -1;
//gfx_s32 _SelStart = properties->_SelStart; //gfx_s32 _SelStart = properties->_SelStart;
//gfx_s32 _SelLen = properties->_SelLen; //gfx_s32 _SelLen = properties->_SelLen;
...@@ -648,14 +653,9 @@ int GI::Display::Display::drawString(char *string, signed int X, signed int Y, t ...@@ -648,14 +653,9 @@ int GI::Display::Display::drawString(char *string, signed int X, signed int Y, t
do do
{ {
gfx_u8 Char = *pcString; gfx_u8 Char = *pcString;
if (lLength >= 0 && CharCnt > lLength)
{
refresh();
return CharCnt - 1;
}
if (Char == 0) if (Char == 0)
{ {
refresh(); //refresh();
return CharCnt - 1; return CharCnt - 1;
} }
#ifdef __AVR_XMEGA__ #ifdef __AVR_XMEGA__
...@@ -691,10 +691,10 @@ int GI::Display::Display::drawString(char *string, signed int X, signed int Y, t ...@@ -691,10 +691,10 @@ int GI::Display::Display::drawString(char *string, signed int X, signed int Y, t
{ {
Tmp = chWidth; Tmp = chWidth;
} }
if (Cursor_X + Tmp >= sClipRegion.sXMin if (Cursor_X + Tmp >= int_box.sXMin
&& Cursor_X < sClipRegion.sXMax + Tmp && Cursor_X < int_box.sXMax + Tmp
&& Cursor_Y + chHeight >= sClipRegion.sYMin && Cursor_Y + chHeight >= int_box.sYMin
&& Cursor_Y < sClipRegion.sYMax + chHeight) && Cursor_Y < int_box.sYMax + chHeight)
{ {
if (ulVisible) if (ulVisible)
{ {
...@@ -749,7 +749,7 @@ int GI::Display::Display::drawString(char *string, signed int X, signed int Y, t ...@@ -749,7 +749,7 @@ int GI::Display::Display::drawString(char *string, signed int X, signed int Y, t
ScreenStruct->CharHeight = chHeight; ScreenStruct->CharHeight = chHeight;
return EOF; return EOF;
}*/ }*/
if ((Cursor_X + chWidth > sClipRegion.sXMax) if ((Cursor_X + chWidth > int_box.sXMax)
&& WordWrap == true) && WordWrap == true)
{ {
Cursor_Y += chHeight; Cursor_Y += chHeight;
......
...@@ -120,6 +120,123 @@ typedef struct FPGA_SPI_struct ...@@ -120,6 +120,123 @@ typedef struct FPGA_SPI_struct
register8_t CTRLB; /* Control Register B */ register8_t CTRLB; /* Control Register B */
} FPGA_SPI_t; } FPGA_SPI_t;
/* SPI Mode */
typedef enum FPGA_SPI_MODE_enum
{
FPGA_SPI_MODE_0_gc = (0x00<<2), /* SPI Mode 0, base clock at "0", sampling on leading edge (rising) & set-up on trailling edge (falling). */
FPGA_SPI_MODE_1_gc = (0x01<<2), /* SPI Mode 1, base clock at "0", set-up on leading edge (rising) & sampling on trailling edge (falling). */
FPGA_SPI_MODE_2_gc = (0x02<<2), /* SPI Mode 2, base clock at "1", sampling on leading edge (falling) & set-up on trailling edge (rising). */
FPGA_SPI_MODE_3_gc = (0x03<<2), /* SPI Mode 3, base clock at "1", set-up on leading edge (falling) & sampling on trailling edge (rising). */
} FPGA_SPI_MODE_t;
/* Prescaler setting */
typedef enum FPGA_SPI_PRESCALER_enum
{
FPGA_SPI_PRESCALER_DIV4_gc = (0x00<<0), /* If CLK2X=1 CLKper/2, else (CLK2X=0) CLKper/4. */
FPGA_SPI_PRESCALER_DIV16_gc = (0x01<<0), /* If CLK2X=1 CLKper/8, else (CLK2X=0) CLKper/16. */
FPGA_SPI_PRESCALER_DIV64_gc = (0x02<<0), /* If CLK2X=1 CLKper/32, else (CLK2X=0) CLKper/64. */
FPGA_SPI_PRESCALER_DIV128_gc = (0x03<<0), /* If CLK2X=1 CLKper/64, else (CLK2X=0) CLKper/128. */
} FPGA_SPI_PRESCALER_t;
/* Interrupt level */
typedef enum FPGA_SPI_INTLVL_enum
{
FPGA_SPI_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */
FPGA_SPI_INTLVL_LO_gc = (0x01<<0), /* Low Level */
FPGA_SPI_INTLVL_MED_gc = (0x02<<0), /* Medium Level */
FPGA_SPI_INTLVL_HI_gc = (0x03<<0), /* High Level */
} FPGA_SPI_INTLVL_t;
/* Buffer Modes */
typedef enum FPGA_SPI_BUFMODE_enum
{
FPGA_SPI_BUFMODE_OFF_gc = (0x00<<6), /* SPI Unbuffered Mode */
FPGA_SPI_BUFMODE_BUFMODE1_gc = (0x02<<6), /* Buffer Mode 1 (with dummy byte) */
FPGA_SPI_BUFMODE_BUFMODE2_gc = (0x03<<6), /* Buffer Mode 2 (no dummy byte) */
} FPGA_SPI_BUFMODE_t;
/* SPI - Serial Peripheral Interface */
/* SPI.CTRL bit masks and bit positions */
#define FPGA_SPI_CLK2X_bm 0x80 /* Enable Double Speed bit mask. */
#define FPGA_SPI_CLK2X_bp 7 /* Enable Double Speed bit position. */
#define FPGA_SPI_ENABLE_bm 0x40 /* Enable SPI Module bit mask. */
#define FPGA_SPI_ENABLE_bp 6 /* Enable SPI Module bit position. */
#define FPGA_SPI_DORD_bm 0x20 /* Data Order Setting bit mask. */
#define FPGA_SPI_DORD_bp 5 /* Data Order Setting bit position. */
#define FPGA_SPI_MASTER_bm 0x10 /* Master Operation Enable bit mask. */
#define FPGA_SPI_MASTER_bp 4 /* Master Operation Enable bit position. */
#define FPGA_SPI_MODE_gm 0x0C /* SPI Mode group mask. */
#define FPGA_SPI_MODE_gp 2 /* SPI Mode group position. */
#define FPGA_SPI_MODE0_bm (1<<2) /* SPI Mode bit 0 mask. */
#define FPGA_SPI_MODE0_bp 2 /* SPI Mode bit 0 position. */
#define FPGA_FPGA_SPI_MODE1_bm (1<<3) /* SPI Mode bit 1 mask. */
#define SPI_MODE1_bp 3 /* SPI Mode bit 1 position. */
#define FPGA_SPI_PRESCALER_gm 0x03 /* Prescaler group mask. */
#define FPGA_SPI_PRESCALER_gp 0 /* Prescaler group position. */
#define FPGA_SPI_PRESCALER0_bm (1<<0) /* Prescaler bit 0 mask. */
#define FPGA_SPI_PRESCALER0_bp 0 /* Prescaler bit 0 position. */
#define FPGA_SPI_PRESCALER1_bm (1<<1) /* Prescaler bit 1 mask. */
#define FPGA_SPI_PRESCALER1_bp 1 /* Prescaler bit 1 position. */
/* SPI.INTCTRL bit masks and bit positions */
#define FPGA_SPI_RXCIE_bm 0x80 /* Receive Complete Interrupt Enable (In Buffer Modes Only). bit mask. */
#define FPGA_SPI_RXCIE_bp 7 /* Receive Complete Interrupt Enable (In Buffer Modes Only). bit position. */
#define FPGA_SPI_TXCIE_bm 0x40 /* Transmit Complete Interrupt Enable (In Buffer Modes Only). bit mask. */
#define FPGA_SPI_TXCIE_bp 6 /* Transmit Complete Interrupt Enable (In Buffer Modes Only). bit position. */
#define FPGA_SPI_DREIE_bm 0x20 /* Data Register Empty Interrupt Enable (In Buffer Modes Only). bit mask. */
#define FPGA_SPI_DREIE_bp 5 /* Data Register Empty Interrupt Enable (In Buffer Modes Only). bit position. */
#define FPGA_SPI_SSIE_bm 0x10 /* Slave Select Trigger Interrupt Enable (In Buffer Modes Only). bit mask. */
#define FPGA_SPI_SSIE_bp 4 /* Slave Select Trigger Interrupt Enable (In Buffer Modes Only). bit position. */
#define FPGA_SPI_INTLVL_gm 0x03 /* Interrupt level group mask. */
#define FPGA_SPI_INTLVL_gp 0 /* Interrupt level group position. */
#define FPGA_SPI_INTLVL0_bm (1<<0) /* Interrupt level bit 0 mask. */
#define FPGA_SPI_INTLVL0_bp 0 /* Interrupt level bit 0 position. */
#define FPGA_SPI_INTLVL1_bm (1<<1) /* Interrupt level bit 1 mask. */
#define FPGA_SPI_INTLVL1_bp 1 /* Interrupt level bit 1 position. */
/* SPI.STATUS bit masks and bit positions */
#define FPGA_SPI_IF_bm 0x80 /* Interrupt Flag (In Standard Mode Only). bit mask. */
#define FPGA_SPI_IF_bp 7 /* Interrupt Flag (In Standard Mode Only). bit position. */
#define FPGA_SPI_RXCIF_bm 0x80 /* Receive Complete Interrupt Flag (In Buffer Modes Only). bit mask. */
#define FPGA_SPI_RXCIF_bp 7 /* Receive Complete Interrupt Flag (In Buffer Modes Only). bit position. */
#define FPGA_SPI_WRCOL_bm 0x40 /* Write Collision Flag (In Standard Mode Only). bit mask. */
#define FPGA_SPI_WRCOL_bp 6 /* Write Collision Flag (In Standard Mode Only). bit position. */
#define FPGA_SPI_TXCIF_bm 0x40 /* Transmit Complete Interrupt Flag (In Buffer Modes Only). bit mask. */
#define FPGA_SPI_TXCIF_bp 6 /* Transmit Complete Interrupt Flag (In Buffer Modes Only). bit position. */
#define FPGA_SPI_DREIF_bm 0x20 /* Data Register Empty Interrupt Flag (In Buffer Modes Only). bit mask. */
#define FPGA_SPI_DREIF_bp 5 /* Data Register Empty Interrupt Flag (In Buffer Modes Only). bit position. */
#define FPGA_SPI_SSIF_bm 0x10 /* Slave Select Trigger Interrupt Flag (In Buffer Modes Only). bit mask. */
#define FPGA_SPI_SSIF_bp 4 /* Slave Select Trigger Interrupt Flag (In Buffer Modes Only). bit position. */
#define FPGA_SPI_BUFOVF_bm 0x01 /* Buffer Overflow (In Buffer Modes Only). bit mask. */
#define FPGA_SPI_BUFOVF_bp 0 /* Buffer Overflow (In Buffer Modes Only). bit position. */
/* SPI.CTRLB bit masks and bit positions */
#define FPGA_SPI_BUFMODE_gm 0xC0 /* Buffer Modes group mask. */
#define FPGA_SPI_BUFMODE_gp 6 /* Buffer Modes group position. */
#define FPGA_SPI_BUFMODE0_bm (1<<6) /* Buffer Modes bit 0 mask. */
#define FPGA_SPI_BUFMODE0_bp 6 /* Buffer Modes bit 0 position. */
#define FPGA_SPI_BUFMODE1_bm (1<<7) /* Buffer Modes bit 1 mask. */
#define FPGA_SPI_BUFMODE1_bp 7 /* Buffer Modes bit 1 position. */
#define FPGA_SPI_SSD_bm 0x04 /* Slave Select Disable bit mask. */
#define FPGA_SPI_SSD_bp 2 /* Slave Select Disable bit position. */
/* /*
-------------------------------------------------------------------------- --------------------------------------------------------------------------
USART - Universal Asynchronous Receiver-Transmitter USART - Universal Asynchronous Receiver-Transmitter
......
...@@ -254,7 +254,7 @@ void GI::Device::Display::Ssd1306::_drawRectangle(void *driverHandlerPtr, signed ...@@ -254,7 +254,7 @@ void GI::Device::Display::Ssd1306::_drawRectangle(void *driverHandlerPtr, signed
_drawPixel(driverHandlerPtr, x, LineCnt, color); _drawPixel(driverHandlerPtr, x, LineCnt, color);
} }
} }
_refresh(driverHandler); //_refresh(driverHandler);
return; return;
} }
int _x_end = x_end; int _x_end = x_end;
...@@ -300,7 +300,7 @@ void GI::Device::Display::Ssd1306::_drawRectangle(void *driverHandlerPtr, signed ...@@ -300,7 +300,7 @@ void GI::Device::Display::Ssd1306::_drawRectangle(void *driverHandlerPtr, signed
//ScreenBuff[(x_end - 1) + (driverHandler->Width * LineCnt)] = _color; //ScreenBuff[(x_end - 1) + (driverHandler->Width * LineCnt)] = _color;
} }
} }
_refresh(driverHandler); //_refresh(driverHandler);
} }
void GI::Device::Display::Ssd1306::_drawHLine(void *driverHandlerPtr, signed int X1, signed int X2, signed int Y, unsigned char width, unsigned int color) void GI::Device::Display::Ssd1306::_drawHLine(void *driverHandlerPtr, signed int X1, signed int X2, signed int Y, unsigned char width, unsigned int color)
...@@ -329,7 +329,7 @@ void GI::Device::Display::Ssd1306::_drawHLine(void *driverHandlerPtr, signed int ...@@ -329,7 +329,7 @@ void GI::Device::Display::Ssd1306::_drawHLine(void *driverHandlerPtr, signed int
for(; _Y_ < Y + Half_width2; _Y_++) for(; _Y_ < Y + Half_width2; _Y_++)
_drawPixel(driverHandler,(unsigned int)(X1_Tmp),(unsigned int)(_Y_), color); _drawPixel(driverHandler,(unsigned int)(X1_Tmp),(unsigned int)(_Y_), color);
} }
_refresh(driverHandler); //_refresh(driverHandler);
} }
void GI::Device::Display::Ssd1306::_drawVLine(void *driverHandlerPtr, signed int Y1, signed int Y2, signed int X, unsigned char width, unsigned int color) void GI::Device::Display::Ssd1306::_drawVLine(void *driverHandlerPtr, signed int Y1, signed int Y2, signed int X, unsigned char width, unsigned int color)
...@@ -358,7 +358,7 @@ void GI::Device::Display::Ssd1306::_drawVLine(void *driverHandlerPtr, signed int ...@@ -358,7 +358,7 @@ void GI::Device::Display::Ssd1306::_drawVLine(void *driverHandlerPtr, signed int
for(; _X_ < X + Half_width2; _X_++) for(; _X_ < X + Half_width2; _X_++)
_drawPixel(driverHandler,(unsigned int)(_X_),(unsigned int)(Y1_Tmp), color); _drawPixel(driverHandler,(unsigned int)(_X_),(unsigned int)(Y1_Tmp), color);
} }
_refresh(driverHandler); //_refresh(driverHandler);
} }
void GI::Device::Display::Ssd1306::_clear(void *driverHandlerPtr, unsigned int color) void GI::Device::Display::Ssd1306::_clear(void *driverHandlerPtr, unsigned int color)
......
...@@ -357,7 +357,7 @@ void GI::Device::Display::Ssd1331::_drawRectangle(void *driverHandlerPtr, signed ...@@ -357,7 +357,7 @@ void GI::Device::Display::Ssd1331::_drawRectangle(void *driverHandlerPtr, signed
driverHandler->wrCmd(cmds, 13); driverHandler->wrCmd(cmds, 13);
volatile u32 cntDelay = (FCPU / 10000000) * (y_end - y_start) * (x_end - x_start); volatile u32 cntDelay = (FCPU / 10000000) * (y_end - y_start) * (x_end - x_start);
while(cntDelay--); while(cntDelay--);
_refresh(driverHandler); //_refresh(driverHandler);
} }
void GI::Device::Display::Ssd1331::_drawHLine(void *driverHandlerPtr, signed int X1, signed int X2, signed int Y, unsigned char width, unsigned int color) void GI::Device::Display::Ssd1331::_drawHLine(void *driverHandlerPtr, signed int X1, signed int X2, signed int Y, unsigned char width, unsigned int color)
...@@ -386,7 +386,7 @@ void GI::Device::Display::Ssd1331::_drawHLine(void *driverHandlerPtr, signed int ...@@ -386,7 +386,7 @@ void GI::Device::Display::Ssd1331::_drawHLine(void *driverHandlerPtr, signed int
for(; _Y_ < Y + Half_width2; _Y_++) for(; _Y_ < Y + Half_width2; _Y_++)
_drawPixel(driverHandler,(unsigned int)(X1_Tmp),(unsigned int)(_Y_), color); _drawPixel(driverHandler,(unsigned int)(X1_Tmp),(unsigned int)(_Y_), color);
} }
_refresh(driverHandler); //_refresh(driverHandler);
} }
void GI::Device::Display::Ssd1331::_drawVLine(void *driverHandlerPtr, signed int Y1, signed int Y2, signed int X, unsigned char width, unsigned int color) void GI::Device::Display::Ssd1331::_drawVLine(void *driverHandlerPtr, signed int Y1, signed int Y2, signed int X, unsigned char width, unsigned int color)
...@@ -415,7 +415,7 @@ void GI::Device::Display::Ssd1331::_drawVLine(void *driverHandlerPtr, signed int ...@@ -415,7 +415,7 @@ void GI::Device::Display::Ssd1331::_drawVLine(void *driverHandlerPtr, signed int
for(; _X_ < X + Half_width2; _X_++) for(; _X_ < X + Half_width2; _X_++)
_drawPixel(driverHandler,(unsigned int)(_X_),(unsigned int)(Y1_Tmp), color); _drawPixel(driverHandler,(unsigned int)(_X_),(unsigned int)(Y1_Tmp), color);
} }
_refresh(driverHandler); //_refresh(driverHandler);
} }
void GI::Device::Display::Ssd1331::_clear(void *driverHandlerPtr, unsigned int color) void GI::Device::Display::Ssd1331::_clear(void *driverHandlerPtr, unsigned int color)
......
This diff is collapsed.
...@@ -82,29 +82,29 @@ GI::Dev::Spi::Spi(ioSettings *cfg) ...@@ -82,29 +82,29 @@ GI::Dev::Spi::Spi(ioSettings *cfg)
BaseAddr->OUTSET = pgm_read_byte(&BIT_MASK_TABLE[int_cfg->cs % 8]); BaseAddr->OUTSET = pgm_read_byte(&BIT_MASK_TABLE[int_cfg->cs % 8]);
BaseAddr->DIRSET = pgm_read_byte(&BIT_MASK_TABLE[int_cfg->cs % 8]);*/ BaseAddr->DIRSET = pgm_read_byte(&BIT_MASK_TABLE[int_cfg->cs % 8]);*/
unsigned char tmp = SPI_MODE_gm & (int_cfg->spiMode << SPI_MODE_gp); unsigned char tmp = FPGA_SPI_MODE_gm & (int_cfg->spiMode << FPGA_SPI_MODE_gp);
u32 new_speed = 0; u32 new_speed = 0;
if(int_cfg->speed > FCPU/2) if(int_cfg->speed > FCPU/2)
new_speed = SPI_CLK2X_bm | SPI_PRESCALER_DIV4_gc; new_speed = FPGA_SPI_CLK2X_bm | FPGA_SPI_PRESCALER_DIV4_gc;
else if(int_cfg->speed > FCPU/4) else if(int_cfg->speed > FCPU/4)
new_speed = SPI_PRESCALER_DIV4_gc; new_speed = FPGA_SPI_PRESCALER_DIV4_gc;
else if(int_cfg->speed > FCPU/8) else if(int_cfg->speed > FCPU/8)
new_speed = SPI_CLK2X_bm | SPI_PRESCALER_DIV16_gc; new_speed = FPGA_SPI_CLK2X_bm | FPGA_SPI_PRESCALER_DIV16_gc;
else if(int_cfg->speed > FCPU/16) else if(int_cfg->speed > FCPU/16)
new_speed = SPI_PRESCALER_DIV16_gc; new_speed = FPGA_SPI_PRESCALER_DIV16_gc;
else if(int_cfg->speed > FCPU/32) else if(int_cfg->speed > FCPU/32)
new_speed = SPI_CLK2X_bm | SPI_PRESCALER_DIV64_gc; new_speed = FPGA_SPI_CLK2X_bm | FPGA_SPI_PRESCALER_DIV64_gc;
else if(int_cfg->speed > FCPU/64) else if(int_cfg->speed > FCPU/64)
new_speed = SPI_PRESCALER_DIV64_gc; new_speed = FPGA_SPI_PRESCALER_DIV64_gc;
else if(int_cfg->speed > FCPU/128) else if(int_cfg->speed > FCPU/128)
new_speed = SPI_PRESCALER_DIV128_gc; new_speed = FPGA_SPI_PRESCALER_DIV128_gc;
else else
new_speed = SPI_PRESCALER_DIV128_gc; new_speed = FPGA_SPI_PRESCALER_DIV128_gc;
tmp |= new_speed; tmp |= new_speed;
if(int_cfg->lsbFirst) if(int_cfg->lsbFirst)
tmp |= SPI_DORD_bm; tmp |= FPGA_SPI_DORD_bm;
tmp |= SPI_ENABLE_bm | SPI_MASTER_bm; tmp |= FPGA_SPI_ENABLE_bm | FPGA_SPI_MASTER_bm;
switch(unitNr) switch(unitNr)
{ {
...@@ -243,7 +243,7 @@ SysErr GI::Dev::Spi::writeRead(unsigned char *buffWrite, unsigned int lenWrite, ...@@ -243,7 +243,7 @@ SysErr GI::Dev::Spi::writeRead(unsigned char *buffWrite, unsigned int lenWrite,
/* Start transmission */ /* Start transmission */
port->DATA = *tmp_buff_ptr++; port->DATA = *tmp_buff_ptr++;
/* Wait for transmission complete */ /* Wait for transmission complete */
while(!(port->STATUS & SPI_IF_bm)) { } while(!(port->STATUS & FPGA_SPI_IF_bm)) { }
//tmp_read = port->DATA; //tmp_read = port->DATA;
} }
tmp_buff_ptr = buffRead; tmp_buff_ptr = buffRead;
...@@ -252,7 +252,7 @@ SysErr GI::Dev::Spi::writeRead(unsigned char *buffWrite, unsigned int lenWrite, ...@@ -252,7 +252,7 @@ SysErr GI::Dev::Spi::writeRead(unsigned char *buffWrite, unsigned int lenWrite,
/* Start transmission */ /* Start transmission */
port->DATA = 0xFF; port->DATA = 0xFF;
/* Wait for transmission complete */ /* Wait for transmission complete */
while(!(port->STATUS & SPI_IF_bm)) { } while(!(port->STATUS & FPGA_SPI_IF_bm)) { }
*tmp_buff_ptr++ = port->DATA; *tmp_buff_ptr++ = port->DATA;
} }
if (!disableCsHandle) if (!disableCsHandle)
...@@ -293,7 +293,7 @@ int GI::Dev::Spi::readBytes(unsigned char *buff, unsigned int len) ...@@ -293,7 +293,7 @@ int GI::Dev::Spi::readBytes(unsigned char *buff, unsigned int len)
/* Start transmission */ /* Start transmission */
port->DATA = 0xFF; port->DATA = 0xFF;
/* Wait for transmission complete */ /* Wait for transmission complete */
while(!(port->STATUS & SPI_IF_bm)) { } while(!(port->STATUS & FPGA_SPI_IF_bm)) { }
*tmp_buff_ptr++ = port->DATA; *tmp_buff_ptr++ = port->DATA;
} }
...@@ -338,7 +338,7 @@ int GI::Dev::Spi::writeBytes(unsigned char *buff, unsigned int len) ...@@ -338,7 +338,7 @@ int GI::Dev::Spi::writeBytes(unsigned char *buff, unsigned int len)
/* Start transmission */ /* Start transmission */
port->DATA = *tmp_buff_ptr++; port->DATA = *tmp_buff_ptr++;
/* Wait for transmission complete */ /* Wait for transmission complete */
while(!(port->STATUS & SPI_IF_bm)) { } while(!(port->STATUS & FPGA_SPI_IF_bm)) { }
tmp_read = port->DATA; tmp_read = port->DATA;
} }
...@@ -366,7 +366,7 @@ SysErr GI::Dev::Spi::writeReadByte(unsigned char *byte) ...@@ -366,7 +366,7 @@ SysErr GI::Dev::Spi::writeReadByte(unsigned char *byte)
/* Start transmission */ /* Start transmission */
port->DATA = *byte; port->DATA = *byte;
/* Wait for transmission complete */ /* Wait for transmission complete */
while(!(port->STATUS & SPI_IF_bm)) { } while(!(port->STATUS & FPGA_SPI_IF_bm)) { }
*byte = port->DATA; *byte = port->DATA;
err = SYS_ERR_OK; err = SYS_ERR_OK;
return SYS_ERR_OK; return SYS_ERR_OK;
...@@ -388,23 +388,23 @@ SysErr GI::Dev::Spi::setSpeed(unsigned long baud) ...@@ -388,23 +388,23 @@ SysErr GI::Dev::Spi::setSpeed(unsigned long baud)
CfgSpi *int_cfg = (CfgSpi *)cfg->cfg; CfgSpi *int_cfg = (CfgSpi *)cfg->cfg;
u32 new_speed = 0; u32 new_speed = 0;
if(int_cfg->speed > FCPU/2) if(int_cfg->speed > FCPU/2)
new_speed = SPI_CLK2X_bm | SPI_PRESCALER_DIV4_gc; new_speed = FPGA_SPI_CLK2X_bm | FPGA_SPI_PRESCALER_DIV4_gc;
else if(int_cfg->speed > FCPU/4) else if(int_cfg->speed > FCPU/4)
new_speed = SPI_PRESCALER_DIV4_gc; new_speed = FPGA_SPI_PRESCALER_DIV4_gc;
else if(int_cfg->speed > FCPU/8) else if(int_cfg->speed > FCPU/8)
new_speed = SPI_CLK2X_bm | SPI_PRESCALER_DIV16_gc; new_speed = FPGA_SPI_CLK2X_bm | FPGA_SPI_PRESCALER_DIV16_gc;
else if(int_cfg->speed > FCPU/16) else if(int_cfg->speed > FCPU/16)
new_speed = SPI_PRESCALER_DIV16_gc; new_speed = FPGA_SPI_PRESCALER_DIV16_gc;
else if(int_cfg->speed > FCPU/32) else if(int_cfg->speed > FCPU/32)
new_speed = SPI_CLK2X_bm | SPI_PRESCALER_DIV64_gc; new_speed = FPGA_SPI_CLK2X_bm | FPGA_SPI_PRESCALER_DIV64_gc;
else if(int_cfg->speed > FCPU/64) else if(int_cfg->speed > FCPU/64)
new_speed = SPI_PRESCALER_DIV64_gc; new_speed = FPGA_SPI_PRESCALER_DIV64_gc;
else if(int_cfg->speed > FCPU/128) else if(int_cfg->speed > FCPU/128)
new_speed = SPI_PRESCALER_DIV128_gc; new_speed = FPGA_SPI_PRESCALER_DIV128_gc;
else else
new_speed = SPI_PRESCALER_DIV128_gc; new_speed = FPGA_SPI_PRESCALER_DIV128_gc;
port->CTRL = (port->CTRL & ~(SPI_CLK2X_bm | SPI_PRESCALER_gm)) | new_speed; port->CTRL = (port->CTRL & ~(FPGA_SPI_CLK2X_bm | FPGA_SPI_PRESCALER_gm)) | new_speed;
err = SYS_ERR_OK; err = SYS_ERR_OK;
return SYS_ERR_OK; return SYS_ERR_OK;
} }
......
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