Commit 9e4b45bc authored by Iulian Gheorghiu's avatar Iulian Gheorghiu

Add TWI support for FPGA_Xmega IP, all devices that support this interface on FPGA now are enabled

parent d5bcaa4a
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......@@ -1160,7 +1160,7 @@ all: $(OUTPUT_FILE_PATH) $(ADDITIONAL_DEPENDENCIES)
$(OUTPUT_FILE_PATH): $(OBJS) $(USER_OBJS) $(OUTPUT_FILE_DEP) $(LIB_DEP) $(LINKER_SCRIPT_DEP)
@echo Building target: $@
@echo Invoking: AVR8/GNU Linker : 4.8.1
$(QUOTE)C:\Program Files (x86)\Atmel\Atmel Toolchain\AVR8 GCC\Native\3.4.1061\avr8-gnu-toolchain\bin\avr-g++.exe$(QUOTE) -o$(OUTPUT_FILE_PATH_AS_ARGS) $(OBJS_AS_ARGS) $(USER_OBJS) $(LIBS) -Wl,-Map="ExampleXmega_FPGA.map" -Wl,--start-group -Wl,-lm -Wl,--end-group -Wl,--gc-sections -mrelax -mmcu=atxmega32e5
$(QUOTE)C:\Program Files (x86)\Atmel\Atmel Toolchain\AVR8 GCC\Native\3.4.1061\avr8-gnu-toolchain\bin\avr-g++.exe$(QUOTE) -o$(OUTPUT_FILE_PATH_AS_ARGS) $(OBJS_AS_ARGS) $(USER_OBJS) $(LIBS) -Wl,-Map="ExampleXmega_FPGA.map" -Wl,-u,vfprintf -Wl,--start-group -Wl,-lm -Wl,--end-group -Wl,--gc-sections -mrelax -mmcu=atxmega32e5
@echo Finished building target: $@
"C:\Program Files (x86)\Atmel\Atmel Toolchain\AVR8 GCC\Native\3.4.1061\avr8-gnu-toolchain\bin\avr-objcopy.exe" -O ihex -R .eeprom -R .fuse -R .lock -R .signature -R .user_signatures "ExampleXmega_FPGA.elf" "ExampleXmega_FPGA.hex"
"C:\Program Files (x86)\Atmel\Atmel Toolchain\AVR8 GCC\Native\3.4.1061\avr8-gnu-toolchain\bin\avr-objcopy.exe" -j .eeprom --set-section-flags=.eeprom=alloc,load --change-section-lma .eeprom=0 --no-change-warnings -O ihex "ExampleXmega_FPGA.elf" "ExampleXmega_FPGA.eep" || exit 0
......
......@@ -164,6 +164,7 @@
<avrgcccpp.compiler.optimization.AllocateBytesNeededForEnum>True</avrgcccpp.compiler.optimization.AllocateBytesNeededForEnum>
<avrgcccpp.compiler.optimization.DebugLevel>Default (-g2)</avrgcccpp.compiler.optimization.DebugLevel>
<avrgcccpp.compiler.warnings.AllWarnings>True</avrgcccpp.compiler.warnings.AllWarnings>
<avrgcccpp.linker.general.UseVprintfLibrary>True</avrgcccpp.linker.general.UseVprintfLibrary>
<avrgcccpp.linker.libraries.Libraries>
<ListValues>
<Value>libm</Value>
......
......@@ -16,7 +16,7 @@
#define UART_INTERFACE_COUNT 1
#define SPI_INTERFACE_COUNT 1
#define SPI_CHANNELS_PER_INTERFACE_COUNT 4
#define TWI_INTERFACE_COUNT 0
#define TWI_INTERFACE_COUNT 1
#define FPGA_RTC (*(FPGA_RTC_t *) 0x0040) /* Port */
......@@ -29,6 +29,7 @@
#define FPGA_PORTG (*(FPGA_PORT_t *) 0x0120) /* Onboard OLED display Port */
#define FPGA_UARTA (*(FPGA_USART_t *) 0x0400) /* */
#define FPGA_SPIA (*(FPGA_SPI_t *) 0x0600) /* */
#define FPGA_TWIA (*(FPGA_TWI_t *) 0x0800) /* */
#define RST_vect _VECTOR(0)
#define RTC_vect _VECTOR(1)
......
......@@ -10,7 +10,7 @@
#define USE_GPIO true
#define USE_UART true
#define USE_I2C false
#define USE_I2C true
#define USE_SPI true
#define USE_SCREEN false
......@@ -60,7 +60,7 @@
//#define _USE_MPL3115A2 "i2c-0"
//#define _USE_MPR121 "i2c-0"
//#define _USE_MPU60x0_9150 "i2c-0"
//#define _USE_LSM9DS1 "i2c-0"
#define _USE_LSM9DS1 "i2c-0"
//#define _USE_LPS25HB "i2c-0"
//#define _USE_MCP79410 "i2c-0"
//#define _USE_TCN75A "i2c-0"
......
......@@ -44,7 +44,7 @@ ioSetCfgGpio(ug2832_vdd, "oled-vdd", pin_mux_convert_to_pin(IOG, 3),CfgGpio::
ioSetCfgUart(uart_0, "uart-0", pin_mux_convert_to_pin(IOA, 0) , pin_mux_convert_to_pin(IOA, 0) , 115200 , CfgUart::WORD_LEN_8 , CfgUart::STOP_BITS_ONE , CfgUart::PAR_NONE , CfgUart::MODE_ASYNC);
//ioSetCfgI2c(i2c_0, "i2c-0", pin_mux_convert_to_pin(IOB, 8), pin_mux_convert_to_pin(IOB, 9), 100000);
ioSetCfgI2c(i2c_0, "i2c-0", pin_mux_convert_to_pin(IOA, 0), pin_mux_convert_to_pin(IOA, 0), 400000);
ioSetCfgSpi(spi_0_0, "spi-0.0", pin_mux_convert_to_pin(IOA, 0), pin_mux_convert_to_pin(IOA, 0), pin_mux_convert_to_pin(IOA, 0), pin_mux_convert_to_pin(IOA, 0), CfgSpi::spiMode0, 5000000, false);
......@@ -77,7 +77,7 @@ ioSettings *ioSetCfg[] = {
&ug2832_vbat,
&ug2832_vdd,
&uart_0,
//&i2c_0,
&i2c_0,
&spi_0_0,
&ioTableEnd,
(ioSettings *)-1/* This is an artifice to force linker to put this structure ito .data section, to be sure that this will be initiated before the call of init() function. */
......
This diff is collapsed.
......@@ -15,29 +15,30 @@
extern CfgI2c i2cCfg[];
TWI_t* I2C_BASE_PTRS[] =
FPGA_TWI_t* I2C_BASE_PTRS[] =
{
#ifdef FPGA_TWIC
&FPGA_TWIC,
#ifdef FPGA_TWIA
&FPGA_TWIA,
#else
NULL,
#endif
#ifdef FPGA_TWID
&FPGA_TWID,
#ifdef FPGA_TWIB
&FPGA_TWIB,
#else
NULL,
#endif
#ifdef FPGA_TWIE
&FPGA_TWIE,
#ifdef FPGA_TWIC
&FPGA_TWIC,
#else
NULL,
#endif
#ifdef FPGA_TWIF
&FPGA_TWIF,
#ifdef FPGA_TWID
&FPGA_TWID,
#else
NULL,
#endif
};
extern unsigned long FCPU;
//#####################################################
/**
......@@ -72,42 +73,72 @@ GI::Dev::I2c::I2c(ioSettings *cfg)
udata = (void *) I2C_BASE_PTRS[dev_nr];
unitNr = dev_nr;
this->cfg = cfg;
//CfgI2c *int_cfg = (CfgI2c *)cfg->cfg;
//I2C_ConfigType sI2C_Config = {0};
/* Initialize I2C module with interrupt mode */
//sI2C_Config.u16Slt = 0;
//sI2C_Config.u16F = 0xBC; /* Baud rate at 100 kbit/sec, MULT = 4 , ICR=60*/
//sI2C_Config.sSetting.bMSTEn=1;
//sI2C_Config.sSetting.bIntEn = 0;
//sI2C_Config.sSetting.bI2CEn = 1;
CfgI2c *int_cfg = (CfgI2c *)cfg->cfg;
//I2C_Init(pI2C[dev_nr], &sI2C_Config);
((FPGA_TWI_t*)udata)->MASTER.BAUD = ((CPU_FREQ / 4) / int_cfg->speed) -1;
((FPGA_TWI_t*)udata)->MASTER.CTRLA = FPGA_TWI_MASTER_ENABLE_bm;
}
/*#####################################################*/
GI::Dev::I2c::~I2c()
{
//I2C_Deinit((I2C_Type *)udata);
((FPGA_TWI_t*)udata)->MASTER.CTRLA &= ~FPGA_TWI_MASTER_ENABLE_bm;
}
SysErr GI::Dev::I2c::WR(unsigned char addr, unsigned char *buff_send,
unsigned int TransmitBytes, unsigned char *buff_receive,
unsigned int ReceiveBytes)
{
//TWI_t *pI2Cx = (TWI_t *)udata;
uint8_t u8ErrorStatus = 0;
if (!noSendWriteOnRead)
unsigned int cnt_bytes;
if(TransmitBytes)
{
((FPGA_TWI_t*)udata)->MASTER.DATA = addr;
while ((((FPGA_TWI_t*)udata)->MASTER.STATUS & FPGA_TWI_MASTER_WIF_bm) == 0);
if(((FPGA_TWI_t*)udata)->MASTER.STATUS & FPGA_TWI_MASTER_RXACK_bm)
{
((FPGA_TWI_t*)udata)->MASTER.CTRLC = FPGA_TWI_MASTER_CMD_STOP_gc;
while ((((FPGA_TWI_t*)udata)->MASTER.CTRLC & FPGA_TWI_MASTER_CMD_gm) != 0);
return SYS_ERR_NAK;
}
for(cnt_bytes = 0; cnt_bytes < TransmitBytes; cnt_bytes++)
{
((FPGA_TWI_t*)udata)->MASTER.DATA = *buff_send++;
while ((((FPGA_TWI_t*)udata)->MASTER.STATUS & FPGA_TWI_MASTER_WIF_bm) == 0);
if(((FPGA_TWI_t*)udata)->MASTER.STATUS & FPGA_TWI_MASTER_RXACK_bm)
{
((FPGA_TWI_t*)udata)->MASTER.CTRLC = FPGA_TWI_MASTER_CMD_STOP_gc;
while ((((FPGA_TWI_t*)udata)->MASTER.CTRLC & FPGA_TWI_MASTER_CMD_gm) != 0);
return SYS_ERR_NAK;
}
}
}
if (!ReceiveBytes)
{
return (SysErr)u8ErrorStatus;
}
else
if(ReceiveBytes)
{
return (SysErr)u8ErrorStatus;
if(TransmitBytes)
{
((FPGA_TWI_t*)udata)->MASTER.CTRLC = FPGA_TWI_MASTER_CMD_REPSTART_gc;
while ((((FPGA_TWI_t*)udata)->MASTER.CTRLC & FPGA_TWI_MASTER_CMD_gm) != 0);
}
((FPGA_TWI_t*)udata)->MASTER.DATA = addr | 0x01;
unsigned char tmp_status;
while ((((FPGA_TWI_t*)udata)->MASTER.STATUS & FPGA_TWI_MASTER_WIF_bm) == 0);
if(((FPGA_TWI_t*)udata)->MASTER.STATUS & FPGA_TWI_MASTER_RXACK_bm)
{
((FPGA_TWI_t*)udata)->MASTER.CTRLC = FPGA_TWI_MASTER_CMD_STOP_gc;
while ((((FPGA_TWI_t*)udata)->MASTER.CTRLC & FPGA_TWI_MASTER_CMD_gm) != 0);
return SYS_ERR_NAK;
}
for(cnt_bytes = 0; cnt_bytes < ReceiveBytes; cnt_bytes++)
{
unsigned char tmp_status;
((FPGA_TWI_t*)udata)->MASTER.CTRLC = FPGA_TWI_MASTER_CMD_RECVTRANS_gc | ((cnt_bytes == ReceiveBytes - 1) ? FPGA_TWI_MASTER_ACKACT_bm : 0 );
while ((((FPGA_TWI_t*)udata)->MASTER.STATUS & FPGA_TWI_MASTER_RIF_bm) == 0);
*buff_receive++ = ((FPGA_TWI_t*)udata)->MASTER.DATA;
}
}
((FPGA_TWI_t*)udata)->MASTER.CTRLC = FPGA_TWI_MASTER_CMD_STOP_gc;
while ((((FPGA_TWI_t*)udata)->MASTER.CTRLC & FPGA_TWI_MASTER_CMD_gm) != 0);
return SYS_ERR_OK;
}
/*#####################################################*/
......
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