Commit 7ad2d0fe authored by Iulian Gheorghiu's avatar Iulian Gheorghiu

Add SPI support for XMEGA_FPGA, using the SPI interface the ATXMEGA DEMO…

Add SPI support for XMEGA_FPGA, using the SPI interface the ATXMEGA DEMO application will initialize and write some symbols on the NEXUS VIDEO internal OLED display.
parent d92266ba
......@@ -343,6 +343,9 @@ void main_app(void)
#ifdef _USE_SSD1331
GI::Device::Display::Ssd1331 *ssd1331_0 = new GI::Device::Display::Ssd1331(_USE_SSD1331);
#endif
#ifdef _USE_SSD1306
GI::Device::Display::Ssd1306 *ssd1306_0 = new GI::Device::Display::Ssd1306(_USE_SSD1306);
#endif
#if (USE_UART == 1 && USE_TERMINAL == 1)
term_cmd = new Cmd((string)CONSOLE_UART_IN, (string)CONSOLE_UART_OUT, (string)CONSOLE_UART_ERR);
......@@ -361,20 +364,20 @@ void main_app(void)
#if (USE_SCREEN == true && USE_SCREEN_GUI == false && SCREENS_COUNT > 0)
/* These functions interact directly with registered driver, the GUI library is not used because the display resolution is too tinny. */
dev.SCREEN[0]->drawPixel(3, 1, ClrWhite);
dev.SCREEN[0]->drawRectangle(1, 3, 5, 5, true, ClrWhite);
dev.SCREEN[0]->drawRectangle(1, 9, 5, 5, false, ClrWhite);
dev.SCREEN[0]->drawHLine(1, 16, 16, 1, ClrWhite);//Optimized linear horizontal line.
dev.SCREEN[0]->drawVLine(18, 10, 8, 1, ClrWhite);//Optimized linear verical line.
dev.SCREEN[0]->drawString((string)"Morgoth CppSDK example application", 16, 0, NULL, true, 0, ClrWhite);
dev.SCREEN[0]->drawCircle(32, 23, 8, 1, ClrWhite);
dev.SCREEN[0]->drawCircle(50, 23, 8, 0, ClrWhite);
dev.SCREEN[0]->drawPixel(3, 1, Color::White);
dev.SCREEN[0]->drawRectangle(1, 3, 5, 5, true, Color::White);
dev.SCREEN[0]->drawRectangle(1, 9, 5, 5, false, Color::White);
dev.SCREEN[0]->drawHLine(1, 16, 16, 1, Color::White);//Optimized linear horizontal line.
dev.SCREEN[0]->drawVLine(18, 10, 8, 1, Color::White);//Optimized linear verical line.
dev.SCREEN[0]->drawString((string)"Morgoth CppSDK example application", 16, 0, NULL, true, 0, Color::White);
dev.SCREEN[0]->drawCircle(32, 23, 8, 1, Color::White);
dev.SCREEN[0]->drawCircle(50, 23, 8, 0, Color::White);
#ifndef SmartRf06// The TI CC1310 compiler has an issue with floating point operations that make the uC to generate a fault interrupt, I think that is a stack problem.
dev.SCREEN[0]->drawElipse(69, 23, 8, 4, 1, ClrWhite);
dev.SCREEN[0]->drawElipse(83, 23, 4, 8, 0, ClrWhite);
dev.SCREEN[0]->drawElipse(69, 23, 8, 4, 1, Color::White);
dev.SCREEN[0]->drawElipse(83, 23, 4, 8, 0, Color::White);
#endif
dev.SCREEN[0]->drawLine(90, 16, 110, 25, 1, ClrWhite);//Complex inclined line.
dev.SCREEN[0]->drawLine(98, 16, 118, 25, 3, ClrWhite);//Complex inclined line.
dev.SCREEN[0]->drawLine(90, 16, 110, 25, 1, Color::White);//Complex inclined line.
dev.SCREEN[0]->drawLine(98, 16, 118, 25, 3, Color::White);//Complex inclined line.
#endif
#ifdef _USE_SSD1331
if(ssd1331_0)/* This display driver is used like an external device (non registered display driver), you can declare more displays in this form, even multiplexed on same SPI interface. */
......@@ -396,6 +399,26 @@ void main_app(void)
ssd1331_0->drawLine(98, 16, 118, 25, 3, Color::Red);//Complex inclined line.
}
#endif
#ifdef _USE_SSD1306
if(ssd1306_0)/* This display driver is used like an external device (non registered display driver), you can declare more displays in this form, even multiplexed on same SPI interface. */
{
ssd1306_0->clear(Color::Black);
ssd1306_0->drawPixel(3, 1, Color::White);
ssd1306_0->drawRectangle(1, 3, 5, 5, true, Color::White);
ssd1306_0->drawRectangle(1, 9, 5, 5, false, Color::White);
ssd1306_0->drawHLine(1, 16, 16, 1, Color::White);//Optimized linear horizontal line.
ssd1306_0->drawVLine(18, 10, 8, 1, Color::White);//Optimized linear verical line.
ssd1306_0->drawString((string)"Morgoth CppSDK example application", 16, 0, NULL, true, Color::Black, Color::White);
ssd1306_0->drawCircle(32, 23, 8, 1, Color::White);
ssd1306_0->drawCircle(50, 23, 8, 0, Color::White);
#ifndef SmartRf06// The TI CC1310 compiler has an issue with floating point operations that make the uC to generate a fault interrupt, I think that is a stack problem.
ssd1306_0->drawElipse(69, 23, 8, 4, 1, Color::White);
ssd1306_0->drawElipse(83, 23, 4, 8, 0, Color::White);
#endif
ssd1306_0->drawLine(90, 16, 110, 25, 1, Color::White);//Complex inclined line.
ssd1306_0->drawLine(98, 16, 118, 25, 3, Color::White);//Complex inclined line.
}
#endif
while(1)
{
......@@ -522,6 +545,9 @@ _continue:
#ifdef _USE_SSD1331
ssd1331_0->drawRectangle(1, 32, 5, 5, true, Color::Black);
#endif
#ifdef _USE_SSD1306
ssd1306_0->drawRectangle(96, 24, 5, 5, true, Color::Black);
#endif
}
else
{
......@@ -530,6 +556,9 @@ _continue:
#ifdef _USE_SSD1331
ssd1331_0->drawRectangle(1, 32, 5, 5, true, Color::Red);
#endif
#ifdef _USE_SSD1306
ssd1306_0->drawRectangle(96, 24, 5, 5, true, Color::White);
#endif
}
}
#ifdef _USE_HIH613x
......
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/*
* ExampleXmega_E5_Xplained.cpp
*
* Created: 4/16/2017 9:44:27 PM
* Author: Cutare
*/
#include <avr/io.h>
int main(void)
{
while(1)
{
//TODO:: Please write your application code
}
}
\ No newline at end of file

Microsoft Visual Studio Solution File, Format Version 11.00
# Atmel Studio Solution File, Format Version 11.00
Project("{E66E83B9-2572-4076-B26E-6BE79FF3018A}") = "ExampleXmega_FPGA", "ExampleXmega_E5_Xplained\ExampleXmega_FPGA.cppproj", "{4BCCA38F-80F4-4515-9BD6-CC6697519C63}"
Project("{E66E83B9-2572-4076-B26E-6BE79FF3018A}") = "ExampleXmega_FPGA", "ExampleXmega_FPGA\ExampleXmega_FPGA.cppproj", "{4BCCA38F-80F4-4515-9BD6-CC6697519C63}"
EndProject
Global
GlobalSection(SolutionConfigurationPlatforms) = preSolution
......
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......@@ -38,7 +38,7 @@
</dependencies>
</framework-data>
</AsfFrameworkConfig>
<avrtool>com.atmel.avrdbg.tool.jtagice3plus</avrtool>
<avrtool>com.atmel.avrdbg.tool.simulator</avrtool>
<avrtoolinterface>PDI</avrtoolinterface>
<com_atmel_avrdbg_tool_ispmk2>
<ToolOptions>
......@@ -54,7 +54,6 @@
<com_atmel_avrdbg_tool_jtagice3plus>
<ToolOptions>
<InterfaceProperties>
<PdiClock>4000000</PdiClock>
</InterfaceProperties>
<InterfaceName>PDI</InterfaceName>
</ToolOptions>
......@@ -62,6 +61,17 @@
<ToolNumber>J30200031349</ToolNumber>
<ToolName>JTAGICE3</ToolName>
</com_atmel_avrdbg_tool_jtagice3plus>
<com_atmel_avrdbg_tool_simulator>
<ToolOptions xmlns="">
<InterfaceProperties>
</InterfaceProperties>
<InterfaceName>PDI</InterfaceName>
</ToolOptions>
<ToolType xmlns="">com.atmel.avrdbg.tool.simulator</ToolType>
<ToolNumber xmlns="">
</ToolNumber>
<ToolName xmlns="">Simulator</ToolName>
</com_atmel_avrdbg_tool_simulator>
</PropertyGroup>
<PropertyGroup Condition=" '$(Configuration)' == 'Release' ">
<ToolchainSettings>
......@@ -162,10 +172,8 @@
<avrgcccpp.assembler.debugging.DebugLevel>Default (-Wa,-g)</avrgcccpp.assembler.debugging.DebugLevel>
</AvrGccCpp>
</ToolchainSettings>
<PreBuildEvent>IntelHexToVerilogMem.exe -i "$(OutputFileName).hex" -o "C:\GitHub\VERILOG-XMEGA-CORE-IP-TST\core1ROM.mem"
IntelHexToVerilogMem.exe -i "$(OutputFileName).hex" -o "C:\GitHub\VERILOG-XMEGA-CORE-IP-TST-LATTICE\core1ROM.mem" -g 2</PreBuildEvent>
<PostBuildEvent>IntelHexToVerilogMem.exe -i "$(OutputFileName).hex" -o "C:\GitHub\VERILOG-XMEGA-CORE-IP-TST\core1ROM.mem"
IntelHexToVerilogMem.exe -i "$(OutputFileName).hex" -o "C:\GitHub\VERILOG-XMEGA-CORE-IP-TST-LATTICE\core1ROM.mem" -g 2</PostBuildEvent>
<PreBuildEvent>IntelHexToVerilogMem.exe -i "$(OutputFileName).hex" -o "C:\GitHub\VERILOG-XMEGA-CORE-IP-TST\core1ROM.mem" -g 2</PreBuildEvent>
<PostBuildEvent>IntelHexToVerilogMem.exe -i "$(OutputFileName).hex" -o "C:\GitHub\VERILOG-XMEGA-CORE-IP-TST\core1ROM.mem" -g 2</PostBuildEvent>
</PropertyGroup>
<ItemGroup>
<Compile Include="..\..\SDK\lib\api\init_def.h">
......
......@@ -14,24 +14,34 @@
#define CPU_FREQ (32000000)
#define UART_INTERFACE_COUNT 1
#define SPI_INTERFACE_COUNT 0
#define SPI_INTERFACE_COUNT 1
#define SPI_CHANNELS_PER_INTERFACE_COUNT 4
#define TWI_INTERFACE_COUNT 0
#define FPGA_RTC (*(FPGA_RTC_t *) 0x0040) /* Virtual Port */
#define FPGA_PORTA (*(FPGA_PORT_t *) 0x0060) /* Virtual Port */
#define FPGA_PORTB (*(FPGA_PORT_t *) 0x0080) /* Virtual Port */
#define FPGA_PORTC (*(FPGA_PORT_t *) 0x00A0) /* Virtual Port */
#define FPGA_UARTA (*(FPGA_USART_t *) 0x00C0) /* Virtual Port */
#define FPGA_RTC (*(FPGA_RTC_t *) 0x0040) /* Port */
#define FPGA_PORTA (*(FPGA_PORT_t *) 0x0060) /* Push buttons Port */
#define FPGA_PORTB (*(FPGA_PORT_t *) 0x0080) /* Switch Port */
#define FPGA_PORTC (*(FPGA_PORT_t *) 0x00A0) /* LED's Port */
#define FPGA_PORTD (*(FPGA_PORT_t *) 0x00C0) /* PMOD A Port */
#define FPGA_PORTE (*(FPGA_PORT_t *) 0x00E0) /* PMOD B Port */
#define FPGA_PORTF (*(FPGA_PORT_t *) 0x0100) /* PMOD C Port */
#define FPGA_PORTG (*(FPGA_PORT_t *) 0x0120) /* Onboard OLED display Port */
#define FPGA_UARTA (*(FPGA_USART_t *) 0x0400) /* */
#define FPGA_SPIA (*(FPGA_SPI_t *) 0x0600) /* */
#define RST_vect _VECTOR(0)
#define RTC_vect _VECTOR(1)
#define PORTA_vect _VECTOR(2)
#define PORTB_vect _VECTOR(3)
#define PORTC_vect _VECTOR(4)
#define UART_A_RXC_vect _VECTOR(5)
#define UART_A_TXC_vect _VECTOR(6)
#define UART_A_DRE_vect _VECTOR(7)
#define PORTD_vect _VECTOR(5)
#define PORTE_vect _VECTOR(6)
#define PORTF_vect _VECTOR(7)
#define SPI_A_vect _VECTOR(8)
#define UART_A_RXC_vect _VECTOR(9)
#define UART_A_TXC_vect _VECTOR(10)
#define UART_A_DRE_vect _VECTOR(11)
......
......@@ -11,7 +11,7 @@
#define USE_GPIO true
#define USE_UART true
#define USE_I2C false
#define USE_SPI false
#define USE_SPI true
#define USE_SCREEN false
#define CALIBRATE_TOUCH_ON_STARTUP false
......@@ -65,6 +65,7 @@
//#define _USE_MCP79410 "i2c-0"
//#define _USE_TCN75A "i2c-0"
//#define _USE_SSD1331 &lcd_UG9664HDDAG01_LANDSCAPE, (string)"spi-0.0", (string)"pc1", (string)"pc13", (string)"pb13", (string)"pb12"
#define _USE_SSD1306 &lcd_UG2832HSWEG04_LANDSCAPE, (string)"spi-0.0", (string)"oled-dc", (string)"oled-res"
/* Need for update */
//#define _USE_MS5611 false
......
......@@ -15,14 +15,11 @@
#include <api/i2c.h>
#include <api/uart.h>
ioSetCfgGpio(led_0, "led-0", pin_mux_convert_to_pin(IOC, 0),CfgGpio::GPIO_OUT_PUSH_PULL, false, false, 0);
ioSetCfgGpio(led_1, "led-1", pin_mux_convert_to_pin(IOC, 1),CfgGpio::GPIO_OUT_PUSH_PULL, false, false, 0);
ioSetCfgGpio(led_2, "led-2", pin_mux_convert_to_pin(IOC, 2),CfgGpio::GPIO_OUT_PUSH_PULL, false, false, 0);
ioSetCfgGpio(led_3, "led-3", pin_mux_convert_to_pin(IOC, 3),CfgGpio::GPIO_OUT_PUSH_PULL, false, false, 0);
ioSetCfgGpio(led_4, "led-4", pin_mux_convert_to_pin(IOC, 4),CfgGpio::GPIO_OUT_PUSH_PULL, false, false, 0);
ioSetCfgGpio(led_5, "led-5", pin_mux_convert_to_pin(IOC, 5),CfgGpio::GPIO_OUT_PUSH_PULL, false, false, 0);
ioSetCfgGpio(led_6, "led-6", pin_mux_convert_to_pin(IOC, 6),CfgGpio::GPIO_OUT_PUSH_PULL, false, false, 0);
ioSetCfgGpio(led_7, "led-7", pin_mux_convert_to_pin(IOC, 7),CfgGpio::GPIO_OUT_PUSH_PULL, false, false, 0);
ioSetCfgGpio(push_0, "phbtn-0", pin_mux_convert_to_pin(IOA, 0),CfgGpio::GPIO_IN_FLOATING, false, false, 0);
ioSetCfgGpio(push_1, "phbtn-1", pin_mux_convert_to_pin(IOA, 1),CfgGpio::GPIO_IN_FLOATING, false, false, 0);
ioSetCfgGpio(push_2, "phbtn-2", pin_mux_convert_to_pin(IOA, 2),CfgGpio::GPIO_IN_FLOATING, false, false, 0);
ioSetCfgGpio(push_3, "phbtn-3", pin_mux_convert_to_pin(IOA, 3),CfgGpio::GPIO_IN_FLOATING, false, false, 0);
ioSetCfgGpio(push_4, "phbtn-4", pin_mux_convert_to_pin(IOA, 4),CfgGpio::GPIO_IN_FLOATING, false, false, 0);
ioSetCfgGpio(sw_0, "hbtn-0", pin_mux_convert_to_pin(IOB, 0),CfgGpio::GPIO_IN_FLOATING, false, false, 0);
ioSetCfgGpio(sw_1, "hbtn-1", pin_mux_convert_to_pin(IOB, 1),CfgGpio::GPIO_IN_FLOATING, false, false, 0);
ioSetCfgGpio(sw_2, "hbtn-2", pin_mux_convert_to_pin(IOB, 2),CfgGpio::GPIO_IN_FLOATING, false, false, 0);
......@@ -31,27 +28,34 @@ ioSetCfgGpio(sw_4, "hbtn-4", pin_mux_convert_to_pin(IOB, 4),CfgGpio::GPIO_I
ioSetCfgGpio(sw_5, "hbtn-5", pin_mux_convert_to_pin(IOB, 5),CfgGpio::GPIO_IN_FLOATING, false, false, 0);
ioSetCfgGpio(sw_6, "hbtn-6", pin_mux_convert_to_pin(IOB, 6),CfgGpio::GPIO_IN_FLOATING, false, false, 0);
ioSetCfgGpio(sw_7, "hbtn-7", pin_mux_convert_to_pin(IOB, 7),CfgGpio::GPIO_IN_FLOATING, false, false, 0);
ioSetCfgGpio(led_0, "led-0", pin_mux_convert_to_pin(IOC, 0),CfgGpio::GPIO_OUT_PUSH_PULL, false, false, 0);
ioSetCfgGpio(led_1, "led-1", pin_mux_convert_to_pin(IOC, 1),CfgGpio::GPIO_OUT_PUSH_PULL, false, false, 0);
ioSetCfgGpio(led_2, "led-2", pin_mux_convert_to_pin(IOC, 2),CfgGpio::GPIO_OUT_PUSH_PULL, false, false, 0);
ioSetCfgGpio(led_3, "led-3", pin_mux_convert_to_pin(IOC, 3),CfgGpio::GPIO_OUT_PUSH_PULL, false, false, 0);
ioSetCfgGpio(led_4, "led-4", pin_mux_convert_to_pin(IOC, 4),CfgGpio::GPIO_OUT_PUSH_PULL, false, false, 0);
ioSetCfgGpio(led_5, "led-5", pin_mux_convert_to_pin(IOC, 5),CfgGpio::GPIO_OUT_PUSH_PULL, false, false, 0);
ioSetCfgGpio(led_6, "led-6", pin_mux_convert_to_pin(IOC, 6),CfgGpio::GPIO_OUT_PUSH_PULL, false, false, 0);
ioSetCfgGpio(led_7, "led-7", pin_mux_convert_to_pin(IOC, 7),CfgGpio::GPIO_OUT_PUSH_PULL, false, false, 0);
//ioSetCfgGpio(ug2832_rst, "lcd-rst", pin_mux_convert_to_pin(IOD, 3),CfgGpio::GPIO_OUT_PUSH_PULL, false, false, 0);
//ioSetCfgGpio(ug2832_cd, "lcd-cd", pin_mux_convert_to_pin(IOR, 0),CfgGpio::GPIO_OUT_PUSH_PULL, false, false, 0);
ioSetCfgGpio(ug2832_dc, "oled-dc", pin_mux_convert_to_pin(IOG, 0),CfgGpio::GPIO_OUT_PUSH_PULL, false, false, 0);
ioSetCfgGpio(ug2832_rst, "oled-res", pin_mux_convert_to_pin(IOG, 1),CfgGpio::GPIO_OUT_PUSH_PULL, false, false, 1);
ioSetCfgGpio(ug2832_vbat, "oled-vba", pin_mux_convert_to_pin(IOG, 2),CfgGpio::GPIO_OUT_PUSH_PULL, false, false, 0);
ioSetCfgGpio(ug2832_vdd, "oled-vdd", pin_mux_convert_to_pin(IOG, 3),CfgGpio::GPIO_OUT_PUSH_PULL, false, false, 0);
//ioSetCfgUart(uart_3, "uart-3", pin_mux_convert_to_pin(IOA, 1) , pin_mux_convert_to_pin(IOA, 1) , 115200 , CfgUart::WORD_LEN_8 , CfgUart::STOP_BITS_ONE , CfgUart::PAR_NONE , CfgUart::MODE_ASYNC);
ioSetCfgUart(uart_0, "uart-0", pin_mux_convert_to_pin(IOA, 0) , pin_mux_convert_to_pin(IOA, 0) , 115200 , CfgUart::WORD_LEN_8 , CfgUart::STOP_BITS_ONE , CfgUart::PAR_NONE , CfgUart::MODE_ASYNC);
//ioSetCfgI2c(i2c_0, "i2c-0", pin_mux_convert_to_pin(IOB, 8), pin_mux_convert_to_pin(IOB, 9), 100000);
//ioSetCfgSpi(spi_0_0, "spi-0.0", pin_mux_convert_to_pin(IOC, 5), pin_mux_convert_to_pin(IOC, 7), pin_mux_convert_to_pin(IOC, 6), pin_mux_convert_to_pin(IOR, 1), CfgSpi::spiMode0, 5000000, false);
ioSetCfgSpi(spi_0_0, "spi-0.0", pin_mux_convert_to_pin(IOA, 0), pin_mux_convert_to_pin(IOA, 0), pin_mux_convert_to_pin(IOA, 0), pin_mux_convert_to_pin(IOA, 0), CfgSpi::spiMode0, 5000000, false);
ioSetCfgEnd(ioTableEnd);
ioSettings *ioSetCfg[] = {
&led_0,
&led_1,
&led_2,
&led_3,
&led_4,
&led_5,
&led_6,
&led_7,
&push_0,
&push_1,
&push_2,
&push_3,
&push_4,
&sw_0,
&sw_1,
&sw_2,
......@@ -60,11 +64,21 @@ ioSettings *ioSetCfg[] = {
&sw_5,
&sw_6,
&sw_7,
//&ug2832_rst,
//&ug2832_cd,
//&uart_3,
&led_0,
&led_1,
&led_2,
&led_3,
&led_4,
&led_5,
&led_6,
&led_7,
&ug2832_dc,
&ug2832_rst,
&ug2832_vbat,
&ug2832_vdd,
&uart_0,
//&i2c_0,
//&spi_0_0,
&spi_0_0,
&ioTableEnd,
(ioSettings *)-1/* This is an artifice to force linker to put this structure ito .data section, to be sure that this will be initiated before the call of init() function. */
};
......
......@@ -64,16 +64,6 @@ typedef enum FPGA_PORT_ISC_enum
} FPGA_PORT_ISC_t;
/* Serial Peripheral Interface with Buffer Modes */
typedef struct FPGA_SPI_struct
{
register8_t CTRL; /* Control Register */
register8_t INTCTRL; /* Interrupt Control Register */
register8_t STATUS; /* Status Register */
register8_t DATA; /* Data Register */
register8_t CTRLB; /* Control Register B */
} FPGA_SPI_t;
/* Two-Wire Interface */
typedef struct FPGA_TWI_MASTER_struct
{
......@@ -117,6 +107,21 @@ typedef struct FPGA_TWI_struct
/*
--------------------------------------------------------------------------
SPI - Serial Pheripheral Interface
--------------------------------------------------------------------------
*/
/* Serial Peripheral Interface with Buffer Modes */
typedef struct FPGA_SPI_struct
{
register8_t CTRL; /* Control Register */
register8_t INTCTRL; /* Interrupt Control Register */
register8_t STATUS; /* Status Register */
register8_t DATA; /* Data Register */
register8_t CTRLB; /* Control Register B */
} FPGA_SPI_t;
/*
--------------------------------------------------------------------------
USART - Universal Asynchronous Receiver-Transmitter
--------------------------------------------------------------------------
*/
......@@ -410,4 +415,56 @@ typedef enum FPGA_USART_PECACT_enum
/* USART_BSEL Predefined. */
/* USART_BSEL Predefined. */
/*
--------------------------------------------------------------------------
LCD - LCD display Interface
--------------------------------------------------------------------------
*/
#define LCD_CTRL 0
#define LCD_H_RES_LOW 1
#define LCD_H_RES_HIGH 2
#define LCD_H_PULSE_WIDTH 3
#define LCD_H_BACK_PORCH 4
#define LCD_H_FRONT_PORCH 5
#define LCD_V_RES_LOW 6
#define LCD_V_RES_HIGH 7
#define LCD_V_PULSE_WIDTH 8
#define LCD_V_BACK_PORCH 9
#define LCD_V_FRONT_PORCH 10
#define LCD_PIXEL_SIZE 11
#define LCD_BASE_ADDR_BYTE0 12
#define LCD_BASE_ADDR_BYTE1 13
#define LCD_BASE_ADDR_BYTE2 14
#define LCD_BASE_ADDR_BYTE3 15
/*
--------------------------------------------------------------------------
GFX_ACCEL - GFX_ACCEL LCD display 2D accelerator interface
--------------------------------------------------------------------------
*/
#define GFX_ACCEL_CMD 16
#define GFX_ACCEL_CLIP_X_MIN_L 18
#define GFX_ACCEL_CLIP_X_MIN_H 19
#define GFX_ACCEL_CLIP_X_MAX_L 20
#define GFX_ACCEL_CLIP_X_MAX_H 21
#define GFX_ACCEL_CLIP_Y_MIN_L 22
#define GFX_ACCEL_CLIP_Y_MIN_H 23
#define GFX_ACCEL_CLIP_Y_MAX_L 24
#define GFX_ACCEL_CLIP_Y_MAX_H 25
#define GFX_ACCEL_BYTE_0 26
#define GFX_ACCEL_BYTE_1 27
#define GFX_ACCEL_BYTE_2 28
#define GFX_ACCEL_BYTE_3 29
#define GFX_ACCEL_CMD_IDLE 0
#define GFX_ACCEL_CMD_VRAM_ACCESS 1
#define GFX_ACCEL_CMD_PIXEL_LOAD 2
#define GFX_ACCEL_CMD_PIXEL 3
#define GFX_ACCEL_CMD_CTRL_ACCESS 4
#define GFX_ACCEL_CMD_FILL_RECT 5
#endif
\ No newline at end of file
......@@ -205,7 +205,7 @@ void GI::Device::Display::Ssd1306::_drawPixel(void *driverHandlerPtr, signed int
X_Limit = driverHandler->LcdTimings->Y;
break;
}
unsigned char *tmp_buff = driverHandler->buff + (((_Y_Coordonate >> 3) * X_Limit) + (_X_Coordonate % X_Limit));
unsigned char *tmp_buff = driverHandler->buff + (((_Y_Coordonate >> 3) * X_Limit) + _X_Coordonate);
#if __AVR_XMEGA__
if (color)
*tmp_buff |= pgm_read_byte(&SSD1306_BIT_MASK_TABLE[_Y_Coordonate & 0x07]);
......@@ -309,11 +309,11 @@ void GI::Device::Display::Ssd1306::_drawHLine(void *driverHandlerPtr, signed int
return;
GI::Device::Display::Ssd1306 *driverHandler = (GI::Device::Display::Ssd1306 *)driverHandlerPtr;
int X1_Tmp = X1, X2_Tmp = X1 + X2;
if(X1_Tmp <= (int)driverHandler->sClipRegion.sXMin)
if(X1_Tmp < (int)driverHandler->sClipRegion.sXMin)
X1_Tmp = (int)driverHandler->sClipRegion.sXMin;
if(X1_Tmp >= (int)driverHandler->sClipRegion.sXMax)
X1_Tmp = (int)driverHandler->sClipRegion.sXMax;
if(X2_Tmp <= (int)driverHandler->sClipRegion.sXMin)
if(X2_Tmp < (int)driverHandler->sClipRegion.sXMin)
X2_Tmp = (int)driverHandler->sClipRegion.sXMin;
if(X2_Tmp >= (int)driverHandler->sClipRegion.sXMax)
X2_Tmp = (int)driverHandler->sClipRegion.sXMax;
......@@ -338,15 +338,15 @@ void GI::Device::Display::Ssd1306::_drawVLine(void *driverHandlerPtr, signed int
return;
GI::Device::Display::Ssd1306 *driverHandler = (GI::Device::Display::Ssd1306 *)driverHandlerPtr;
int Y1_Tmp = Y1, Y2_Tmp = Y1 + Y2;
if(X <= (int)driverHandler->sClipRegion.sXMin)
if(X < (int)driverHandler->sClipRegion.sXMin)
X = (int)driverHandler->sClipRegion.sXMin;
if(X >= (int)driverHandler->sClipRegion.sXMax)
X = (int)driverHandler->sClipRegion.sXMax;
if(Y1_Tmp <= (int)driverHandler->sClipRegion.sYMin)
if(Y1_Tmp < (int)driverHandler->sClipRegion.sYMin)
Y1_Tmp = (int)driverHandler->sClipRegion.sYMin;
if(Y1_Tmp >= (int)driverHandler->sClipRegion.sYMax)
Y1_Tmp = (int)driverHandler->sClipRegion.sYMax;
if(Y2_Tmp <= (int)driverHandler->sClipRegion.sYMin)
if(Y2_Tmp < (int)driverHandler->sClipRegion.sYMin)
Y2_Tmp = (int)driverHandler->sClipRegion.sYMin;
if(Y2_Tmp >= (int)driverHandler->sClipRegion.sYMax)
Y2_Tmp = (int)driverHandler->sClipRegion.sYMax;
......
......@@ -366,11 +366,11 @@ void GI::Device::Display::Ssd1331::_drawHLine(void *driverHandlerPtr, signed int
return;
GI::Device::Display::Ssd1331 *driverHandler = (GI::Device::Display::Ssd1331 *)driverHandlerPtr;
int X1_Tmp = X1, X2_Tmp = X1 + X2;
if(X1_Tmp <= (int)driverHandler->sClipRegion.sXMin)
if(X1_Tmp < (int)driverHandler->sClipRegion.sXMin)
X1_Tmp = (int)driverHandler->sClipRegion.sXMin;
if(X1_Tmp >= (int)driverHandler->sClipRegion.sXMax)
X1_Tmp = (int)driverHandler->sClipRegion.sXMax - 1;
if(X2_Tmp <= (int)driverHandler->sClipRegion.sXMin)
if(X2_Tmp < (int)driverHandler->sClipRegion.sXMin)
X2_Tmp = (int)driverHandler->sClipRegion.sXMin;
if(X2_Tmp >= (int)driverHandler->sClipRegion.sXMax)
X2_Tmp = (int)driverHandler->sClipRegion.sXMax - 1;
......@@ -399,11 +399,11 @@ void GI::Device::Display::Ssd1331::_drawVLine(void *driverHandlerPtr, signed int
X = (int)driverHandler->sClipRegion.sXMin;
if(X >= (int)driverHandler->sClipRegion.sXMax)
X = (int)driverHandler->sClipRegion.sXMax - 1;
if(Y1_Tmp <= (int)driverHandler->sClipRegion.sYMin)
if(Y1_Tmp < (int)driverHandler->sClipRegion.sYMin)
Y1_Tmp = (int)driverHandler->sClipRegion.sYMin;
if(Y1_Tmp >= (int)driverHandler->sClipRegion.sYMax)
Y1_Tmp = (int)driverHandler->sClipRegion.sYMax - 1;
if(Y2_Tmp <= (int)driverHandler->sClipRegion.sYMin)
if(Y2_Tmp < (int)driverHandler->sClipRegion.sYMin)
Y2_Tmp = (int)driverHandler->sClipRegion.sYMin;
if(Y2_Tmp >= (int)driverHandler->sClipRegion.sYMax)
Y2_Tmp = (int)driverHandler->sClipRegion.sYMax - 1;
......
......@@ -17,23 +17,23 @@ extern CfgI2c i2cCfg[];
TWI_t* I2C_BASE_PTRS[] =
{
#ifdef TWIC
&TWIC,
#ifdef FPGA_TWIC
&FPGA_TWIC,
#else
NULL,
#endif
#ifdef TWID
&TWID,
#ifdef FPGA_TWID
&FPGA_TWID,
#else
NULL,
#endif
#ifdef TWIE
&TWIE,
#ifdef FPGA_TWIE
&FPGA_TWIE,
#else
NULL,
#endif
#ifdef TWIF
&TWIF,
#ifdef FPGA_TWIF
&FPGA_TWIF,
#else
NULL,
#endif
......
......@@ -20,25 +20,25 @@ extern CfgSpi spiCfg[];
volatile bool spi_semaphore[SPI_INTERFACE_COUNT];
#endif
SPI_t* SPI_BASE_PTRS[] =
FPGA_SPI_t* SPI_BASE_PTRS[] =
{
#ifdef SPIC
&SPIC,
#ifdef FPGA_SPIA
&FPGA_SPIA,
#else
NULL,
#endif
#ifdef SPID
&SPID,
#ifdef FPGA_SPIB
&FPGA_SPIB,
#else
NULL,
#endif
#ifdef SPIE
&SPIE,
#ifdef FPGA_SPIC
&FPGA_SPIC,
#else
NULL,
#endif
#ifdef SPIF
&SPIF,
#ifdef FPGA_SPID
&FPGA_SPID,
#else
NULL,
#endif
......@@ -78,9 +78,9 @@ GI::Dev::Spi::Spi(ioSettings *cfg)
this->cfg = cfg;
CfgSpi *int_cfg = (CfgSpi *)cfg->cfg;
volatile FPGA_PORT_t *BaseAddr = GPIO_BASE_PTRS[int_cfg->cs >> 5];
/*volatile FPGA_PORT_t *BaseAddr = GPIO_BASE_PTRS[int_cfg->cs >> 5];
BaseAddr->OUTSET = pgm_read_byte(&BIT_MASK_TABLE[int_cfg->cs % 8]);
BaseAddr->DIRSET = pgm_read_byte(&BIT_MASK_TABLE[int_cfg->cs % 8]);
BaseAddr->DIRSET = pgm_read_byte(&BIT_MASK_TABLE[int_cfg->cs % 8]);*/
unsigned char tmp = SPI_MODE_gm & (int_cfg->spiMode << SPI_MODE_gp);
......@@ -108,40 +108,40 @@ GI::Dev::Spi::Spi(ioSettings *cfg)
switch(unitNr)
{
#ifdef SPIC
#ifdef FPGA_SPIA
case 0:
PORTC.DIRSET = (1 << 4) | (1 << 5) | (1 << 7);
PORTC.OUTSET = (1 << 4) | (1 << 5) | (1 << 7);
PORTC.PIN6CTRL = PORT_OPC_PULLUP_gc;
PORTC.DIRCLR = 1 << 6;
SPIC.CTRL = tmp;
//PORTC.DIRSET = (1 << 4) | (1 << 5) | (1 << 7);
//PORTC.OUTSET = (1 << 4) | (1 << 5) | (1 << 7);
//PORTC.PIN6CTRL = PORT_OPC_PULLUP_gc;
//PORTC.DIRCLR = 1 << 6;
FPGA_SPIA.CTRL = tmp;
break;
#endif
#ifdef SPID
#ifdef FPGA_SPIB
case 1:
PORTD.DIRSET = (1 << 4) | (1 << 5) | (1 << 7);
PORTD.OUTSET = (1 << 4) | (1 << 5) | (1 << 7);
PORTD.PIN6CTRL = PORT_OPC_PULLUP_gc;
PORTD.DIRCLR = 1 << 6;
SPID.CTRL = tmp;
//PORTD.DIRSET = (1 << 4) | (1 << 5) | (1 << 7);
//PORTD.OUTSET = (1 << 4) | (1 << 5) | (1 << 7);
//PORTD.PIN6CTRL = PORT_OPC_PULLUP_gc;
//PORTD.DIRCLR = 1 << 6;
FPGA_SPIB.CTRL = tmp;
break;
#endif
#ifdef SPIE
#ifdef FPGA_SPIC
case 2:
PORTE.DIRSET = (1 << 4) | (1 << 5) | (1 << 7);
PORTE.OUTSET = (1 << 4) | (1 << 5) | (1 << 7);
PORTE.PIN6CTRL = PORT_OPC_PULLUP_gc;
PORTE.DIRCLR = 1 << 6;
SPIE.CTRL = tmp;
//PORTE.DIRSET = (1 << 4) | (1 << 5) | (1 << 7);
//PORTE.OUTSET = (1 << 4) | (1 << 5) | (1 << 7);
//PORTE.PIN6CTRL = PORT_OPC_PULLUP_gc;
//PORTE.DIRCLR = 1 << 6;
FPGA_SPIC.CTRL = tmp;
break;
#endif
#ifdef SPIF
#ifdef FPGA_SPID
case 3:
PORTF.DIRSET = (1 << 4) | (1 << 5) | (1 << 7);
PORTF.OUTSET = (1 << 4) | (1 << 5) | (1 << 7);
PORTF.PIN6CTRL = PORT_OPC_PULLUP_gc;
PORTF.DIRCLR = 1 << 6;
SPIF.CTRL = tmp;
//PORTF.DIRSET = (1 << 4) | (1 << 5) | (1 << 7);
//PORTF.OUTSET = (1 << 4) | (1 << 5) | (1 << 7);
//PORTF.PIN6CTRL = PORT_OPC_PULLUP_gc;
//PORTF.DIRCLR = 1 << 6;
FPGA_SPID.CTRL = tmp;
break;
#endif
}
......@@ -232,7 +232,7 @@ SysErr GI::Dev::Spi::writeRead(unsigned char *buffWrite, unsigned int lenWrite,
BaseAddr->OUTCLR = pgm_read_byte(&BIT_MASK_TABLE[int_cfg->cs % 8]);
}
SysErr status = SYS_ERR_OK;
SPI_t *port = (SPI_t *) userData;
FPGA_SPI_t *port = (FPGA_SPI_t *) userData;
memset(buffRead, 0, lenRead);
unsigned int cnt = 0;
......@@ -285,7 +285,7 @@ int GI::Dev::Spi::readBytes(unsigned char *buff, unsigned int len)
BaseAddr->OUTCLR = pgm_read_byte(&BIT_MASK_TABLE[int_cfg->cs % 8]);
}
SysErr status = SYS_ERR_OK;
SPI_t *port = (SPI_t *) userData;
FPGA_SPI_t *port = (FPGA_SPI_t *) userData;
unsigned int cnt = 0;
unsigned char *tmp_buff_ptr = buff;
for(cnt = 0; cnt < len; cnt++)
......@@ -329,17 +329,17 @@ int GI::Dev::Spi::writeBytes(unsigned char *buff, unsigned int len)
BaseAddr->OUTCLR = pgm_read_byte(&BIT_MASK_TABLE[int_cfg->cs % 8]);
}
SysErr status = SYS_ERR_OK;
SPI_t *port = (SPI_t *) userData;
FPGA_SPI_t *port = (FPGA_SPI_t *) userData;
unsigned int cnt = 0;
unsigned char *tmp_buff_ptr = buff;
//unsigned char tmp_read;
unsigned char tmp_read;
for(; cnt < len; cnt++)
{
/* Start transmission */