Commit 54aa2c9b authored by Iulian Gheorghiu's avatar Iulian Gheorghiu

Fix initialization of global static variables.

parent 16baf393
......@@ -14,7 +14,7 @@
</extensions>
</storageModule>
<storageModule moduleId="cdtBuildSystem" version="4.0.0">
<configuration artifactName="${ProjName}" buildArtefactType="org.eclipse.cdt.build.core.buildArtefactType.exe" buildProperties="org.eclipse.cdt.build.core.buildArtefactType=org.eclipse.cdt.build.core.buildArtefactType.exe,org.eclipse.cdt.build.core.buildType=org.eclipse.cdt.build.core.buildType.debug" cleanCommand="${cross_rm} -rf" description="" errorParsers="org.eclipse.cdt.core.GASErrorParser;org.eclipse.cdt.core.GmakeErrorParser;org.eclipse.cdt.core.GLDErrorParser;org.eclipse.cdt.core.CWDLocator;org.eclipse.cdt.core.GCCErrorParser" id="ilg.gnumcueclipse.managedbuild.cross.riscv.config.elf.debug.2116291671" name="Debug" optionalBuildProperties="org.eclipse.cdt.docker.launcher.containerbuild.property.enablement=null,org.eclipse.cdt.docker.launcher.containerbuild.property.selectedvolumes=,org.eclipse.cdt.docker.launcher.containerbuild.property.volumes=,org.eclipse.cdt.docker.launcher.containerbuild.property.image=null,org.eclipse.cdt.docker.launcher.containerbuild.property.connection=null" parent="ilg.gnumcueclipse.managedbuild.cross.riscv.config.elf.debug" postbuildStep="&quot;D:\eclipse_risc_v\RISC-V Embedded GCC\7.2.0-4-20180606-1631\bin\riscv-none-embed-objdump.exe&quot; -h -S &quot;${PWD}/ExampleRiscFive_FPGA.elf&quot; &gt; &quot;${PWD}/ExampleRiscFive_FPGA.lss&quot;&amp;&quot;${PWD}/IntelHexToVerilogMem.exe&quot; -i &quot;${PWD}\ExampleRiscFive_FPGA.hex&quot; -o &quot;C:\GitHub\VERILOG-RISC-V-LIGHT\core1ROM.mem&quot; -g &quot;4&quot; -b &quot;0x800000&quot;">
<configuration artifactName="${ProjName}" buildArtefactType="org.eclipse.cdt.build.core.buildArtefactType.exe" buildProperties="org.eclipse.cdt.build.core.buildArtefactType=org.eclipse.cdt.build.core.buildArtefactType.exe,org.eclipse.cdt.build.core.buildType=org.eclipse.cdt.build.core.buildType.debug" cleanCommand="${cross_rm} -rf" description="" errorParsers="org.eclipse.cdt.core.GASErrorParser;org.eclipse.cdt.core.GmakeErrorParser;org.eclipse.cdt.core.GLDErrorParser;org.eclipse.cdt.core.CWDLocator;org.eclipse.cdt.core.GCCErrorParser" id="ilg.gnumcueclipse.managedbuild.cross.riscv.config.elf.debug.2116291671" name="Debug" optionalBuildProperties="org.eclipse.cdt.docker.launcher.containerbuild.property.enablement=null,org.eclipse.cdt.docker.launcher.containerbuild.property.selectedvolumes=,org.eclipse.cdt.docker.launcher.containerbuild.property.volumes=,org.eclipse.cdt.docker.launcher.containerbuild.property.image=null,org.eclipse.cdt.docker.launcher.containerbuild.property.connection=null" parent="ilg.gnumcueclipse.managedbuild.cross.riscv.config.elf.debug" postbuildStep="&quot;D:\eclipse_risc_v\RISC-V Embedded GCC\7.2.0-4-20180606-1631\bin\riscv-none-embed-objdump.exe&quot; -h -S &quot;${PWD}/ExampleRiscFive_FPGA.elf&quot; &gt; &quot;${PWD}/ExampleRiscFive_FPGA.lss&quot;&amp;&quot;D:\eclipse_risc_v\RISC-V Embedded GCC\7.2.0-4-20180606-1631\bin\riscv-none-embed-objcopy.exe&quot; -O ihex -j .text -j .data &quot;${PWD}/ExampleRiscFive_FPGA.elf&quot; &quot;${PWD}/ExampleRiscFive_FPGA.hex&quot;&amp;&quot;${PWD}/IntelHexToVerilogMem.exe&quot; -i &quot;${PWD}\ExampleRiscFive_FPGA.hex&quot; -o &quot;C:\GitHub\VERILOG-RISC-V-LIGHT-CORE-IP-TST-XILINX\core1ROM.mem&quot; -g &quot;4&quot; -b &quot;0x800000&quot;">
<folderInfo id="ilg.gnumcueclipse.managedbuild.cross.riscv.config.elf.debug.2116291671." name="/" resourcePath="">
<toolChain id="ilg.gnumcueclipse.managedbuild.cross.riscv.toolchain.elf.debug.1550356398" name="RISC-V Cross GCC" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.toolchain.elf.debug">
<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.addtools.createflash.783561632" name="Create flash image" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.addtools.createflash" useByScannerDiscovery="false" value="true" valueType="boolean"/>
......@@ -86,6 +86,7 @@
</option>
<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.cpp.linker.usenewlibnano.884243281" name="Use newlib-nano (--specs=nano.specs)" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.cpp.linker.usenewlibnano" useByScannerDiscovery="false" value="true" valueType="boolean"/>
<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.cpp.linker.usenewlibnosys.775364165" name="Do not use syscalls (--specs=nosys.specs)" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.cpp.linker.usenewlibnosys" useByScannerDiscovery="false" value="false" valueType="boolean"/>
<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.cpp.linker.nostart.494721154" name="Do not use standard start files (-nostartfiles)" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.cpp.linker.nostart" useByScannerDiscovery="false" value="false" valueType="boolean"/>
<inputType id="ilg.gnumcueclipse.managedbuild.cross.riscv.tool.cpp.linker.input.1817168083" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.tool.cpp.linker.input">
<additionalInput kind="additionalinputdependency" paths="$(USER_OBJS)"/>
<additionalInput kind="additionalinput" paths="$(LIBS)"/>
......
......@@ -31,11 +31,6 @@
<locationURI>virtual:/virtual</locationURI>
</link>
<link>
<name>README.md</name>
<type>1</type>
<locationURI>PARENT-2-PROJECT_LOC/VERILOG-RISC-V-LIGHT/README.md</locationURI>
</link>
<link>
<name>lib</name>
<type>2</type>
<locationURI>virtual:/virtual</locationURI>
......
......@@ -4,18 +4,15 @@ ENTRY(_entry)
MEMORY
{
envm (rx) : ORIGIN = 0x800000, LENGTH = 64k
ram (rwx) : ORIGIN = 0x400000, LENGTH = 16k
ROM (rx) : ORIGIN = 0x800000, LENGTH = 64k
RAM (rwx) : ORIGIN = 0x400000, LENGTH = 16k
}
RAM_START_ADDRESS = ORIGIN(ram); /* Must be the same value MEMORY region ram ORIGIN above. */
RAM_SIZE = LENGTH(ram); /* Must be the same value MEMORY region ram LENGTH above. */
SDATA_SIZE = 2K; /* needs to be calculated for your application */
RAM_START_ADDRESS = ORIGIN(RAM); /* Must be the same value MEMORY region RAM ORIGIN above. */
RAM_SIZE = LENGTH(RAM); /* Must be the same value MEMORY region RAM LENGTH above. */
/*. Highest address of the stack. Used in startup file .*/
__stack_top = ORIGIN(ram) + LENGTH(ram); /*end of SRAM .*/
/*. Generate a link error if heap and stack dont fit into RAM .*/
__stack = ORIGIN(RAM) + LENGTH(RAM);
__stack_size = DEFINED(__stack_size) ? __stack_size : 2K;
SECTIONS
{
......@@ -59,79 +56,109 @@ SECTIONS
PROVIDE_HIDDEN (__fini_array_end = .);
. = ALIGN(0x10);
} >envm
/* short/global data section */
.sdata : ALIGN(0x10)
{
__ram_start = .;
__sdata_load = LOADADDR(.sdata);
__sdata_start = .;
PROVIDE( __global_pointer$ = . + SDATA_SIZE);
__global_pointer = .;
*(.srodata.cst16) *(.srodata.cst8) *(.srodata.cst4) *(.srodata.cst2)
*(.srodata*)
*(.sdata .sdata.* .gnu.linkonce.s.*)
. = ALIGN(0x10);
__sdata_end = .;
} >ram AT>envm
/* data section */
.data : ALIGN(0x10)
{
__data_load = LOADADDR(.data);
__data_start = .;
*(.got.plt) *(.got)
*(.shdata)
*(.data .data.* .gnu.linkonce.d.*)
. = ALIGN(0x10);
__data_end = .;
__edata = __data_end;
} >ram AT>envm
_edata = .;
_sdata_size = SDATA_SIZE;
} >ROM
.data : ALIGN(4)
{
FILL(0xFF)
__data_start__ = . ; /* Standard newlib definition. */
__data_begin__ = . ; /* µOS++ specific */
*(.data_begin .data_begin.*) /* µOS++ __data_begin_guard */
*(.data .data.*)
*(.gnu.linkonce.d.*)
. = ALIGN(8);
/*
* RISC-V specific; the compiler optimises memory accesses
* in the +/- 2K range around __global_pointer$ to GP relative.
* For this to work, GP must be loaded during startup with the
* address of __global_pointer$.
* This optimisation favours a 4K range. Newlib places
* several impure and malloc pointers in the .sdata section.
*/
PROVIDE( __global_pointer$ = . + (4K / 2) );
*(.sdata .sdata.*)
*(.gnu.linkonce.s.*)
/* RISC-V specific; not sure if needed. */
. = ALIGN(8);
*(.srodata.cst16)
*(.srodata.cst8)
*(.srodata.cst4)
*(.srodata.cst2)
*(.srodata .srodata.*)
*(.data_end .data_end.*) /* µOS++ __data_end_guard; must be last */
. = ALIGN(4);
__data_end__ = . ; /* Standard newlib definition. */
} >RAM AT>ROM
/*
* This address is used by the µOS++ startup code to
* initialise the .data section.
*/
__data_load_addr__ = LOADADDR(.data);
. = ALIGN(4);
PROVIDE( __edata = . );
PROVIDE( _edata = . );
PROVIDE( edata = . );
/* The primary uninitialised data section. */
.bss (NOLOAD) : ALIGN(4)
{
__bss_start = .; /* Standard newlib definition. */
__bss_start__ = .; /* Standard newlib definition. */
__bss_begin__ = .; /* µOS++ specific */
*(.bss_begin .bss_begin.*) /* µOS++ __bss_begin_guard */
*(.sbss .sbss.*)
*(.gnu.linkonce.sb.*)
*(.bss .bss.*)
*(.gnu.linkonce.b.*)
*(COMMON)
*(.bss_end .bss_end.*) /* µOS++ __bss_end_guard; must be last */
. = ALIGN(4);
__bss_end__ = .; /* Standard newlib definition. */
__bss_end = .; /* Standard newlib definition. */
} >RAM AT>RAM
/*
* Similar to .bss, but not initialised to zero. µOS++ extension.
*/
.noinit (NOLOAD) : ALIGN(4)
{
__noinit_begin__ = .; /* µOS++ extension. */
*(.noinit .noinit.*)
. = ALIGN(4) ;
__noinit_end__ = .; /* µOS++ extension. */
} >RAM AT>RAM
/* sbss section */
.sbss : ALIGN(0x10)
{
__sbss_start = .;
*(.sbss .sbss.* .gnu.linkonce.sb.*)
*(.scommon)
. = ALIGN(0x10);
__sbss_end = .;
} > ram
/* sbss section */
.bss : ALIGN(0x10)
{
__bss_start = .;
*(.shbss)
*(.bss .bss.* .gnu.linkonce.b.*)
*(COMMON)
. = ALIGN(0x10);
__bss_end = .;
} > ram
_Min_Stack_Size = 1k;
_Min_Heap_Size = (LENGTH(ram) - (__bss_end - ORIGIN(ram)) - _Min_Stack_Size);
/* End of uninitialized data segment */
_end = .;
/* User_heap_stack section, used to check that there is enough RAM left */
.heap : ALIGN(0x10)
{
PROVIDE ( end = . );
PROVIDE ( _end = . );
__heap_start = .;
. = . + _Min_Heap_Size;
__heap_end = .;
. = . + _Min_Stack_Size;
. = ALIGN(0x10);
_heap_end = __heap_end;
} >ram
/* _sbrk() expects at least word alignment. */
. = ALIGN(8);
PROVIDE( __end = . );
PROVIDE( _end = . );
PROVIDE( end = . );
PROVIDE( __heap_begin__ = . ); /* µOS++ extension. */
.stack __stack - __stack_size :
{
PROVIDE( _heap_end = . ); /* Standard newlib definition. */
PROVIDE( __heap_end__ = . ); /* µOS++ extension. */
. += __stack_size;
} >RAM AT>RAM
/* Remove information from the compiler libraries */
/DISCARD/ :
......
......@@ -14,7 +14,7 @@
/**********************************************************************************************
* Global variables
**********************************************************************************************/
unsigned long FCPU = CORE_CLOCK_DEFAULT;
//unsigned long FCPU = CORE_CLOCK_DEFAULT;
/**********************************************************************************************
* Constants and macros
......
......@@ -15,7 +15,7 @@
#endif
_entry:
xor tp, tp, tp
/* xor tp, tp, tp
xor ra, ra, ra
xor t1, t1, t1
xor t2, t2, t2
......@@ -43,11 +43,21 @@ _entry:
xor t3, t3, t3
xor t4, t4, t4
xor t5, t5, t5
xor t6, t6, t6
la gp, __sdata_start
la t0, _sdata_size
add gp,gp,t0
la sp, __stack_top - 4
xor t6, t6, t6*/
.option push
// Ensure the instruction is not optimized, since gp is not yet set.
.option norelax
// __global_pointer$ is a magic symbol, known by the linker.
// Unless instructed not to do so, the linker optimizes
// accesses +/- 2KB around this to gp-relative.
la gp, __global_pointer$
.option pop
// The linker script usually defines the stack at the end of RAM.
la sp, __stack
// Proceed with the standard standard _begin() routine.
j _begin
......
......@@ -14,6 +14,7 @@ extern "C" {
// Macro for weak symbol aliasing
//
//*****************************************************************************
extern int IRQHandler_RTC(unsigned int int_nr);
extern int (* const intVectors[])(unsigned int);
ISR(IRQHandler)
......@@ -54,7 +55,7 @@ ISR(IRQHandler)
"sw x31,32*4(sp)" "\n\t"
"sw x0,1*4(sp)" "\n\t" /* Store Interrupt number*/
"sw x0,0*4(sp)" "\n\t" /* Store return address*/
"xor t0, t0, t0" "\n\t"
/*"xor t0, t0, t0" "\n\t"
"xor t1, t1, t1" "\n\t"
"xor t2, t2, t2" "\n\t"
"xor s0, s0, s0" "\n\t"
......@@ -81,7 +82,7 @@ ISR(IRQHandler)
"xor t3, t3, t3" "\n\t"
"xor t4, t4, t4" "\n\t"
"xor t5, t5, t5" "\n\t"
"xor t6, t6, t6" "\n\t"
"xor t6, t6, t6" "\n\t"*/
);
int interrupt_nr;
__asm__ __volatile__ (
......
......@@ -12,27 +12,21 @@
#include <stdlib.h>
#include <stdint.h>
#include <unistd.h>
#include <io_defs.h>
#ifdef __cplusplus
extern "C" {
#endif
extern uint32_t __sdata_load;
extern uint32_t __sdata_start;
extern uint32_t __sdata_end;
unsigned long FCPU = CPU_FREQ;
extern uint32_t __data_load;
extern uint32_t __data_start;
extern uint32_t __data_end;
extern uint32_t __data_load_addr__;
extern uint32_t __data_start__;
extern uint32_t __data_end__;
extern uint32_t __sbss_start;
extern uint32_t __sbss_end;
extern uint32_t __bss_start;
extern uint32_t __bss_end;
extern uint32_t __heap_start;
extern uint32_t __heap_end;
static void copy_section(uint32_t * p_load, uint32_t * p_vma, uint32_t * p_vma_end)
{
......@@ -57,26 +51,11 @@ static void zero_section(uint32_t * start, uint32_t * end)
void _begin(void)
{
//extern int main(int, char**);
//const char *argv0 = "hello";
//char *argv[] = {(char *)argv0, NULL, NULL};
copy_section(&__sdata_load, &__sdata_start, &__sdata_end);
copy_section(&__data_load, &__data_start, &__data_end);
zero_section(&__sbss_start, &__sbss_end);
copy_section(&__data_load_addr__, &__data_start__, &__data_end__);
zero_section(&__bss_start, &__bss_end);
zero_section(&__heap_start, &__heap_end);
//main(1, argv);
asm volatile ("j _start");
}
/* Function called after main() finishes */
/*void
_fini()
{
}*/
#ifdef __cplusplus
}
#endif
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