Commit 2e5c79f4 authored by Iulian Gheorghiu's avatar Iulian Gheorghiu

Continue to add support for ATXMEGA FPGA controller

parent 666ba7bb
......@@ -286,7 +286,7 @@ void main_app(void)
#if(_USE_PASSWORD_PROTECTION == 1)
newWindowPasswordNumeric(MainWindow, pass, 2, 2);
#endif
#endif/*!(USE_SCREEN_GUI == 1)*/
#endif/*!(USE_SCREEN_GUI == true)*/
/*
* Put on parent window caption the IP of ETH interface.
*/
......
This source diff could not be displayed because it is too large. You can view the blob instead.
......@@ -127,7 +127,7 @@
<Value>..</Value>
</ListValues>
</avrgcc.compiler.directories.IncludePaths>
<avrgcc.compiler.optimization.level>Optimize (-O1)</avrgcc.compiler.optimization.level>
<avrgcc.compiler.optimization.level>Optimize for size (-Os)</avrgcc.compiler.optimization.level>
<avrgcc.compiler.optimization.PackStructureMembers>True</avrgcc.compiler.optimization.PackStructureMembers>
<avrgcc.compiler.optimization.AllocateBytesNeededForEnum>True</avrgcc.compiler.optimization.AllocateBytesNeededForEnum>
<avrgcc.compiler.optimization.DebugLevel>Default (-g2)</avrgcc.compiler.optimization.DebugLevel>
......@@ -149,7 +149,7 @@
<Value>..</Value>
</ListValues>
</avrgcccpp.compiler.directories.IncludePaths>
<avrgcccpp.compiler.optimization.level>Optimize (-O1)</avrgcccpp.compiler.optimization.level>
<avrgcccpp.compiler.optimization.level>Optimize for size (-Os)</avrgcccpp.compiler.optimization.level>
<avrgcccpp.compiler.optimization.PackStructureMembers>True</avrgcccpp.compiler.optimization.PackStructureMembers>
<avrgcccpp.compiler.optimization.AllocateBytesNeededForEnum>True</avrgcccpp.compiler.optimization.AllocateBytesNeededForEnum>
<avrgcccpp.compiler.optimization.DebugLevel>Default (-g2)</avrgcccpp.compiler.optimization.DebugLevel>
......@@ -162,8 +162,16 @@
<avrgcccpp.assembler.debugging.DebugLevel>Default (-Wa,-g)</avrgcccpp.assembler.debugging.DebugLevel>
</AvrGccCpp>
</ToolchainSettings>
<PreBuildEvent>IntelHexToVerilogMem.exe -i "$(OutputFileName).hex" -o "C:\GitHub\VERILOG-XMEGA-CORE-IP-TST\core1ROM.mem"
IntelHexToVerilogMem.exe -i "$(OutputFileName).hex" -o "C:\GitHub\VERILOG-XMEGA-CORE-IP-TST-LATTICE\core1ROM.mem" -g 2</PreBuildEvent>
<PostBuildEvent>IntelHexToVerilogMem.exe -i "$(OutputFileName).hex" -o "C:\GitHub\VERILOG-XMEGA-CORE-IP-TST\core1ROM.mem"
IntelHexToVerilogMem.exe -i "$(OutputFileName).hex" -o "C:\GitHub\VERILOG-XMEGA-CORE-IP-TST-LATTICE\core1ROM.mem" -g 2</PostBuildEvent>
</PropertyGroup>
<ItemGroup>
<Compile Include="..\..\SDK\lib\api\init_def.h">
<SubType>compile</SubType>
<Link>lib\api\init_def.h</Link>
</Compile>
<Compile Include="..\..\SDK\lib\api\lcd.cpp">
<SubType>compile</SubType>
<Link>lib\api\lcd.cpp</Link>
......
......@@ -9,19 +9,29 @@
#ifndef IO_DEFS_H_
#define IO_DEFS_H_
#include "board.h"
#include "board/ATMEL//Xmega-FPGA/xio.h"
#include <board/ATMEL/Xmega-FPGA/xio.h>
#define CPU_FREQ (32000000)
#define CPU_FREQ (32000000)
#define UART_INTERFACE_COUNT 0
#define SPI_INTERFACE_COUNT 0
#define TWI_INTERFACE_COUNT 0
#define UART_INTERFACE_COUNT 0
#define SPI_INTERFACE_COUNT 0
#define SPI_CHANNELS_PER_INTERFACE_COUNT 4
#define TWI_INTERFACE_COUNT 0
#define FPGA_RTC (*(FPGA_RTC_t *) 0x0040) /* Virtual Port */
#define FPGA_PORTA (*(FPGA_PORT_t *) 0x0060) /* Virtual Port */
#define FPGA_PORTB (*(FPGA_PORT_t *) 0x0080) /* Virtual Port */
#define FPGA_RTC (*(FPGA_RTC_t *) 0x0040) /* Virtual Port */
#define FPGA_PORTA (*(FPGA_PORT_t *) 0x0060) /* Virtual Port */
#define FPGA_PORTB (*(FPGA_PORT_t *) 0x0080) /* Virtual Port */
#define FPGA_PORTC (*(FPGA_PORT_t *) 0x00A0) /* Virtual Port */
#define FPGA_UARTA (*(FPGA_USART_t *) 0x00C0) /* Virtual Port */
#define RTC_vect _VECTOR(1)
#define PORTA_vect _VECTOR(2)
#define PORTB_vect _VECTOR(3)
#define PORTC_vect _VECTOR(4)
#define UART_A_RXC_vect _VECTOR(5)
#define UART_A_TXC_vect _VECTOR(6)
#define UART_A_DRE_vect _VECTOR(7)
......
......@@ -9,10 +9,10 @@
#define MAIN_H_
#define USE_GPIO true
#define USE_UART true
#define USE_UART false
#define USE_I2C false
#define USE_SPI true
#define USE_SCREEN true
#define USE_SPI false
#define USE_SCREEN false
#define CALIBRATE_TOUCH_ON_STARTUP false
......
......@@ -39,17 +39,17 @@ GI::Board::Init::Init()
io_item->ioConstruct = (void *)new GI::Dev::Gpio(io_item);
break;
#endif
#if (USE_UART == true)
#if (USE_UART == true && UART_INTERFACE_COUNT != 0)
case ioSettings::info_s::ioType_UART:
io_item->ioConstruct = (void *)new GI::Dev::Uart(io_item);
break;
#endif
#if (USE_I2C == true)
#if (USE_I2C == true && TWI_INTERFACE_COUNT != 0)
case ioSettings::info_s::ioType_I2C:
io_item->ioConstruct = (void *)new GI::Dev::I2c(io_item);
break;
#endif
#if (USE_SPI == true)
#if (USE_SPI == true && SPI_INTERFACE_COUNT != 0)
case ioSettings::info_s::ioType_SPI:
io_item->ioConstruct = (void *)new GI::Dev::Spi(io_item);
break;
......@@ -65,7 +65,7 @@ GI::Board::Init::Init()
*/
#if (defined(SCREEN_CONFIG_1) && defined(USED_SCREEN_CONTROLLER_1) && (SCREENS_COUNT > 0))
SCREEN[0] = new GI::Device::Display::USED_SCREEN_CONTROLLER_1(&SCREEN_CONFIG_1, OTHER_SCREEN_1_PARAMS);
#ifdef USED_TOUCHSCREEN_1
#ifdef USED_TOUCHSCREEN_1 && TOUCH_SCREEN_ENABLE == true
CURSORCTRL[0] = new GI::Device::Cursor::USED_TOUCHSCREEN_1(SCREEN[0], (char *)CAP_TOUCHSCREEN_I2C_UNIT, (char *)CAP_TOUCHSCREEN_IRQ_PIN);
CURSORCTRL[0]->touchCalibrate();
#endif
......
......@@ -15,13 +15,25 @@
#include <api/i2c.h>
#include <api/uart.h>
ioSetCfgGpio(led_0, "led-0", pin_mux_convert_to_pin(IOD, 4),CfgGpio::GPIO_OUT_PUSH_PULL, false, true, 0);
ioSetCfgGpio(led_1, "led-1", pin_mux_convert_to_pin(IOD, 5),CfgGpio::GPIO_OUT_PUSH_PULL, false, true, 0);
ioSetCfgGpio(hbtn_0, "hbtn-0", pin_mux_convert_to_pin(IOD, 0),CfgGpio::GPIO_IN_FLOATING, false, true, 0);
ioSetCfgGpio(hbtn_1, "hbtn-1", pin_mux_convert_to_pin(IOD, 2),CfgGpio::GPIO_IN_FLOATING, false, true, 0);
ioSetCfgGpio(led_0, "led-0", pin_mux_convert_to_pin(IOC, 0),CfgGpio::GPIO_OUT_PUSH_PULL, false, false, 0);
ioSetCfgGpio(led_1, "led-1", pin_mux_convert_to_pin(IOC, 1),CfgGpio::GPIO_OUT_PUSH_PULL, false, false, 0);
ioSetCfgGpio(led_2, "led-2", pin_mux_convert_to_pin(IOC, 2),CfgGpio::GPIO_OUT_PUSH_PULL, false, false, 0);
ioSetCfgGpio(led_3, "led-3", pin_mux_convert_to_pin(IOC, 3),CfgGpio::GPIO_OUT_PUSH_PULL, false, false, 0);
ioSetCfgGpio(led_4, "led-4", pin_mux_convert_to_pin(IOC, 4),CfgGpio::GPIO_OUT_PUSH_PULL, false, false, 0);
ioSetCfgGpio(led_5, "led-5", pin_mux_convert_to_pin(IOC, 5),CfgGpio::GPIO_OUT_PUSH_PULL, false, false, 0);
ioSetCfgGpio(led_6, "led-6", pin_mux_convert_to_pin(IOC, 6),CfgGpio::GPIO_OUT_PUSH_PULL, false, false, 0);
ioSetCfgGpio(led_7, "led-7", pin_mux_convert_to_pin(IOC, 7),CfgGpio::GPIO_OUT_PUSH_PULL, false, false, 0);
ioSetCfgGpio(sw_0, "hbtn-0", pin_mux_convert_to_pin(IOB, 0),CfgGpio::GPIO_IN_FLOATING, false, false, 0);
ioSetCfgGpio(sw_1, "hbtn-1", pin_mux_convert_to_pin(IOB, 1),CfgGpio::GPIO_IN_FLOATING, false, false, 0);
ioSetCfgGpio(sw_2, "hbtn-2", pin_mux_convert_to_pin(IOB, 2),CfgGpio::GPIO_IN_FLOATING, false, false, 0);
ioSetCfgGpio(sw_3, "hbtn-3", pin_mux_convert_to_pin(IOB, 3),CfgGpio::GPIO_IN_FLOATING, false, false, 0);
ioSetCfgGpio(sw_4, "hbtn-4", pin_mux_convert_to_pin(IOB, 4),CfgGpio::GPIO_IN_FLOATING, false, false, 0);
ioSetCfgGpio(sw_5, "hbtn-5", pin_mux_convert_to_pin(IOB, 5),CfgGpio::GPIO_IN_FLOATING, false, false, 0);
ioSetCfgGpio(sw_6, "hbtn-6", pin_mux_convert_to_pin(IOB, 6),CfgGpio::GPIO_IN_FLOATING, false, false, 0);
ioSetCfgGpio(sw_7, "hbtn-7", pin_mux_convert_to_pin(IOB, 7),CfgGpio::GPIO_IN_FLOATING, false, false, 0);
ioSetCfgGpio(ug2832_rst, "lcd-rst", pin_mux_convert_to_pin(IOD, 3),CfgGpio::GPIO_OUT_PUSH_PULL, false, false, 0);
ioSetCfgGpio(ug2832_cd, "lcd-cd", pin_mux_convert_to_pin(IOR, 0),CfgGpio::GPIO_OUT_PUSH_PULL, false, false, 0);
//ioSetCfgGpio(ug2832_rst, "lcd-rst", pin_mux_convert_to_pin(IOD, 3),CfgGpio::GPIO_OUT_PUSH_PULL, false, false, 0);
//ioSetCfgGpio(ug2832_cd, "lcd-cd", pin_mux_convert_to_pin(IOR, 0),CfgGpio::GPIO_OUT_PUSH_PULL, false, false, 0);
//ioSetCfgUart(uart_3, "uart-3", pin_mux_convert_to_pin(IOA, 1) , pin_mux_convert_to_pin(IOA, 1) , 115200 , CfgUart::WORD_LEN_8 , CfgUart::STOP_BITS_ONE , CfgUart::PAR_NONE , CfgUart::MODE_ASYNC);
......@@ -34,10 +46,22 @@ ioSetCfgEnd(ioTableEnd);
ioSettings *ioSetCfg[] = {
&led_0,
&led_1,
&hbtn_0,
&hbtn_1,
&ug2832_rst,
&ug2832_cd,
&led_2,
&led_3,
&led_4,
&led_5,
&led_6,
&led_7,
&sw_0,
&sw_1,
&sw_2,
&sw_3,
&sw_4,
&sw_5,
&sw_6,
&sw_7,
//&ug2832_rst,
//&ug2832_cd,
//&uart_3,
//&i2c_0,
//&spi_0_0,
......
......@@ -4,37 +4,12 @@
#if defined(Xmega_FPGA)
#include <include/global.h>
#include <board/ATMEL/Xmega-FPGA/ffconf.h>
#include <board/ATMEL/Xmega-FPGA/lwipopts.h>
#include "ffconf.h"
#include "lwipopts.h"
#include "xio.h"
#include <io_defs.h>
/*
* Processor choose
*/
//#define STM32F405xx
//#define STM32F415xx
//#define STM32F407xx
//#define STM32F417xx
//#define STM32F427xx
//#define STM32F437xx
//#define STM32F429xx
//#define STM32F439xx
//#define STM32F401xC
//#define STM32F401xE
//#define STM32F410Tx
//#define STM32F410Cx
//#define STM32F410Rx
//#define STM32F411xE
//#define STM32F446xx
#define STM32F469xx
//#define STM32F479xx
/*
* !Processor choose
*/
/*
* Processor clock selection.
*
* If EXTERNAL_CLOCK_VALUE id !0 the reference clock will be EXTERNAL_CLOCK_VALUE.
......@@ -63,10 +38,10 @@
* Screen settings
*/
#define SCREENS_COUNT 1
/*#define SCREENS_COUNT 1
#define SCREEN_CONFIG_1 lcd_UG2832HSWEG04_LANDSCAPE_FLIP
#define USED_SCREEN_CONTROLLER_1 Ssd1306
#define OTHER_SCREEN_1_PARAMS (string)"spi-0.0", (string)"lcd-cd", (string)"lcd-rst"
#define OTHER_SCREEN_1_PARAMS (string)"spi-0.0", (string)"lcd-cd", (string)"lcd-rst"*/
/*
* !Screen settings
......
......@@ -3,7 +3,11 @@
#include <avr/io.h>
/* RTC counter */
/*
--------------------------------------------------------------------------
RTC - Real-Time Clounter
--------------------------------------------------------------------------
*/
typedef struct FPGA_RTC_struct
{
register8_t RTC_CNT_BYTE0;
......@@ -16,34 +20,49 @@ typedef struct FPGA_RTC_struct
register8_t RTC_PERIOD_BYTE3;
} FPGA_RTC_t;
/* I/O Ports */
/*
--------------------------------------------------------------------------
PORT - Port Configuration
--------------------------------------------------------------------------
*/
typedef struct FPGA_PORT_struct
{
register8_t DIR; /* I/O Port Data Direction */
register8_t DIRSET; /* I/O Port Data Direction Set */
register8_t DIRCLR; /* I/O Port Data Direction Clear */
register8_t DIRTGL; /* I/O Port Data Direction Toggle */
register8_t OUT; /* I/O Port Output */
register8_t OUTSET; /* I/O Port Output Set */
register8_t OUTCLR; /* I/O Port Output Clear */
register8_t OUTTGL; /* I/O Port Output Toggle */
register8_t IN; /* I/O port Input */
register8_t INTCTRL; /* Interrupt Control Register */
register8_t INTMASK; /* Port Interrupt Mask */
register8_t reserved_0x0B;
register8_t INTFLAGS; /* Interrupt Flag Register */
register8_t reserved_0x0D;
register8_t REMAP; /* Pin Remap Register */
register8_t reserved_0x0F;
register8_t PIN0CTRL; /* Pin 0 Control Register */
register8_t PIN1CTRL; /* Pin 1 Control Register */
register8_t PIN2CTRL; /* Pin 2 Control Register */
register8_t PIN3CTRL; /* Pin 3 Control Register */
register8_t PIN4CTRL; /* Pin 4 Control Register */
register8_t PIN5CTRL; /* Pin 5 Control Register */
register8_t PIN6CTRL; /* Pin 6 Control Register */
register8_t PIN7CTRL; /* Pin 7 Control Register */
register8_t DIR; /* I/O Port Data Direction */
register8_t DIRSET; /* I/O Port Data Direction Set */
register8_t DIRCLR; /* I/O Port Data Direction Clear */
register8_t DIRTGL; /* I/O Port Data Direction Toggle */
register8_t OUT; /* I/O Port Output */
register8_t OUTSET; /* I/O Port Output Set */
register8_t OUTCLR; /* I/O Port Output Clear */
register8_t OUTTGL; /* I/O Port Output Toggle */
register8_t IN; /* I/O port Input */
register8_t INTCTRL; /* Interrupt Control Register */
register8_t INTMASK; /* Port Interrupt Mask */
register8_t reserved_0x0B;
register8_t INTFLAGS; /* Interrupt Flag Register */
register8_t reserved_0x0D;
register8_t REMAP; /* Pin Remap Register */
register8_t reserved_0x0F;
register8_t PIN0CTRL; /* Pin 0 Control Register */
register8_t PIN1CTRL; /* Pin 1 Control Register */
register8_t PIN2CTRL; /* Pin 2 Control Register */
register8_t PIN3CTRL; /* Pin 3 Control Register */
register8_t PIN4CTRL; /* Pin 4 Control Register */
register8_t PIN5CTRL; /* Pin 5 Control Register */
register8_t PIN6CTRL; /* Pin 6 Control Register */
register8_t PIN7CTRL; /* Pin 7 Control Register */
} FPGA_PORT_t;
/* Input/Sense Configuration */
typedef enum FPGA_PORT_ISC_enum
{
FPGA_PORT_ISC_BOTHEDGES_gc = (0x00<<0), /* Sense Both Edges */
FPGA_PORT_ISC_RISING_gc = (0x01<<0), /* Sense Rising Edge */
FPGA_PORT_ISC_FALLING_gc = (0x02<<0), /* Sense Falling Edge */
FPGA_PORT_ISC_LEVEL_gc = (0x03<<0), /* Sense Level (Transparent For Events) */
FPGA_PORT_ISC_FORCE_ENABLE_gc = (0x06<<0), /* Digital Input Buffer Forced Enable */
FPGA_PORT_ISC_INPUT_DISABLE_gc = (0x07<<0), /* Disable Digital Input Buffer */
} FPGA_PORT_ISC_t;
/* Serial Peripheral Interface with Buffer Modes */
typedef struct FPGA_SPI_struct
......@@ -96,6 +115,12 @@ typedef struct FPGA_TWI_struct
FPGA_TWI_TIMEOUT_t TIMEOUT; /* TWI SMBUS timeout module */
} FPGA_TWI_t;
/*
--------------------------------------------------------------------------
USART - Universal Asynchronous Receiver-Transmitter
--------------------------------------------------------------------------
*/
/* Universal Synchronous/Asynchronous Receiver/Transmitter */
typedef struct FPGA_USART_struct
{
......@@ -109,5 +134,117 @@ typedef struct FPGA_USART_struct
register8_t BAUDCTRLB; /* Baud Rate Control Register B */
} FPGA_USART_t;
/* USART.CTRLA bit masks and bit positions */
/* Receive Start Interrupt level */
typedef enum FPGA_USART_RXSINTLVL_enum
{
FPGA_USART_RXSINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */
FPGA_USART_RXSINTLVL_LO_gc = (0x01<<0), /* Low Level */
FPGA_USART_RXSINTLVL_MED_gc = (0x02<<0), /* Medium Level */
FPGA_USART_RXSINTLVL_HI_gc = (0x03<<0), /* High Level */
} FPGA_USART_RXSINTLVL_t;
/* Receive Complete Interrupt level */
typedef enum FPGA_USART_RXCINTLVL_enum
{
FPGA_USART_RXCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */
FPGA_USART_RXCINTLVL_LO_gc = (0x01<<4), /* Low Level */
FPGA_USART_RXCINTLVL_MED_gc = (0x02<<4), /* Medium Level */
FPGA_USART_RXCINTLVL_HI_gc = (0x03<<4), /* High Level */
} FPGA_USART_RXCINTLVL_t;
/* Transmit Complete Interrupt level */
typedef enum FPGA_USART_TXCINTLVL_enum
{
FPGA_USART_TXCINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */
FPGA_USART_TXCINTLVL_LO_gc = (0x01<<2), /* Low Level */
FPGA_USART_TXCINTLVL_MED_gc = (0x02<<2), /* Medium Level */
FPGA_USART_TXCINTLVL_HI_gc = (0x03<<2), /* High Level */
} FPGA_USART_TXCINTLVL_t;
/* Data Register Empty Interrupt level */
typedef enum FPGA_USART_DREINTLVL_enum
{
FPGA_USART_DREINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */
FPGA_USART_DREINTLVL_LO_gc = (0x01<<0), /* Low Level */
FPGA_USART_DREINTLVL_MED_gc = (0x02<<0), /* Medium Level */
FPGA_USART_DREINTLVL_HI_gc = (0x03<<0), /* High Level */
} FPGA_USART_DREINTLVL_t;
/* USART.CTRLB bit masks and bit positions */
#define FPGA_USART_ONEWIRE_bm 0x80 /* One Wire Mode bit mask. */
#define FPGA_USART_ONEWIRE_bp 7 /* One Wire Mode bit position. */
#define FPGA_USART_SFDEN_bm 0x40 /* Start Frame Detection Enable bit mask. */
#define FPGA_USART_SFDEN_bp 6 /* Start Frame Detection Enable bit position. */
#define FPGA_USART_RXEN_bm 0x10 /* Receiver Enable bit mask. */
#define FPGA_USART_RXEN_bp 4 /* Receiver Enable bit position. */
#define FPGA_USART_TXEN_bm 0x08 /* Transmitter Enable bit mask. */
#define FPGA_USART_TXEN_bp 3 /* Transmitter Enable bit position. */
#define FPGA_USART_CLK2X_bm 0x04 /* Double transmission speed bit mask. */
#define FPGA_USART_CLK2X_bp 2 /* Double transmission speed bit position. */
#define FPGA_USART_MPCM_bm 0x02 /* Multi-processor Communication Mode bit mask. */
#define FPGA_USART_MPCM_bp 1 /* Multi-processor Communication Mode bit position. */
#define FPGA_USART_TXB8_bm 0x01 /* Transmit bit 8 bit mask. */
#define FPGA_USART_TXB8_bp 0 /* Transmit bit 8 bit position. */
/* USART.CTRLC bit masks and bit positions */
/* Character Size */
typedef enum FPGA_USART_CHSIZE_enum
{
FPGA_USART_CHSIZE_5BIT_gc = (0x00<<0), /* Character size: 5 bit */
FPGA_USART_CHSIZE_6BIT_gc = (0x01<<0), /* Character size: 6 bit */
FPGA_USART_CHSIZE_7BIT_gc = (0x02<<0), /* Character size: 7 bit */
FPGA_USART_CHSIZE_8BIT_gc = (0x03<<0), /* Character size: 8 bit */
FPGA_USART_CHSIZE_9BIT_gc = (0x07<<0), /* Character size: 9 bit */
} FPGA_USART_CHSIZE_t;
/* Communication Mode */
typedef enum FPGA_USART_CMODE_enum
{
FPGA_USART_CMODE_ASYNCHRONOUS_gc = (0x00<<6), /* Asynchronous Mode */
FPGA_USART_CMODE_SYNCHRONOUS_gc = (0x01<<6), /* Synchronous Mode */
FPGA_USART_CMODE_IRDA_gc = (0x02<<6), /* IrDA Mode */
FPGA_USART_CMODE_MSPI_gc = (0x03<<6), /* Master SPI Mode */
} FPGA_USART_CMODE_t;
/* Parity Mode */
typedef enum FPGA_USART_PMODE_enum
{
FPGA_USART_PMODE_DISABLED_gc = (0x00<<4), /* No Parity */
FPGA_USART_PMODE_EVEN_gc = (0x02<<4), /* Even Parity */
FPGA_USART_PMODE_ODD_gc = (0x03<<4), /* Odd Parity */
} FPGA_USART_PMODE_t;
/* Encoding and Decoding Type */
typedef enum FPGA_USART_DECTYPE_enum
{
FPGA_USART_DECTYPE_DATA_gc = (0x00<<4), /* DATA Field Encoding */
FPGA_USART_DECTYPE_SDATA_gc = (0x02<<4), /* Start and Data Fields Encoding */
FPGA_USART_DECTYPE_NOTSDATA_gc = (0x03<<4), /* Start and Data Fields Encoding, with invertion in START field */
} FPGA_USART_DECTYPE_t;
/* XCL LUT Action */
typedef enum FPGA_USART_LUTACT_enum
{
FPGA_USART_LUTACT_OFF_gc = (0x00<<2), /* Standard Frame Configuration */
FPGA_USART_LUTACT_RX_gc = (0x01<<2), /* Receiver Decoding Enabled */
FPGA_USART_LUTACT_TX_gc = (0x02<<2), /* Transmitter Encoding Enabled */
FPGA_USART_LUTACT_BOTH_gc = (0x03<<2), /* Both Encoding and Decoding Enabled */
} FPGA_USART_LUTACT_t;
/* XCL Peripheral Counter Action */
typedef enum FPGA_USART_PECACT_enum
{
FPGA_USART_PECACT_OFF_gc = (0x00<<0), /* Standard Mode */
FPGA_USART_PECACT_PEC0_gc = (0x01<<0), /* Variable Data Lenght in Reception */
FPGA_USART_PECACT_PEC1_gc = (0x02<<0), /* Variable Data Lenght in Transmission */
FPGA_USART_PECACT_PERC01_gc = (0x03<<0), /* Variable Data Lenght in both Reception and Transmission */
} FPGA_USART_PECACT_t;
#endif
\ No newline at end of file
......@@ -9,6 +9,7 @@
#define NXP_KEAZ_INTERFACE_I2C_H_
#include <avr/io.h>
#include <io_defs.h>
......
......@@ -9,9 +9,9 @@
#define NXP_KEAZ_INTERFACE_SPI_H_
#include <avr/io.h>
#include <io_defs.h>
#define SPI_CHANNELS_PER_INTERFACE_COUNT 4
......
......@@ -10,6 +10,7 @@
#include <include/global.h>
#include <avr/io.h>
#include <io_defs.h>
#define UART_HAVE_MODE_SYNCHRONOUS 0
#define UART_HAVE_MODE_SPI 0
......
......@@ -7,9 +7,11 @@
#include <avr/io.h>
#include <avr/interrupt.h>
#include <io_defs.h>
#include <sys/systime.h>
GI::Sys::Systime systime = GI::Sys::Systime();
//extern unsigned long FCPU;
#define RTC_PERIOD (CPU_FREQ / 1000)
/******************************************************************************
** INTERNAL VARIABLE DEFINITIONS
*******************************************************************************/
......@@ -19,20 +21,18 @@ volatile unsigned long long STimerCnt = 0;
GI::Sys::Systime::Systime()
{
asm("sei");
unsigned char pmic_reg = PMIC.CTRL;
pmic_reg |= PMIC_HILVLEN_bm;
PROTECTED_WRITE(PMIC.CTRL, pmic_reg);
RTC.PER = 9;
RTC.COMP = 9;
RTC.CTRL = RTC_PRESCALER_DIV1_gc;
RTC.INTCTRL = RTC_OVFINTLVL_HI_gc;
RTC.INTFLAGS = RTC_OVFIF_bm;
CLK.RTCCTRL = CLK_RTCSRC_RCOSC_gc | CLK_RTCEN_bm;
FPGA_RTC.RTC_PERIOD_BYTE3 = (unsigned char)(RTC_PERIOD >> 24);
FPGA_RTC.RTC_PERIOD_BYTE2 = (unsigned char)(RTC_PERIOD >> 16);
FPGA_RTC.RTC_PERIOD_BYTE1 = (unsigned char)(RTC_PERIOD >> 8);
FPGA_RTC.RTC_PERIOD_BYTE0 = (unsigned char)RTC_PERIOD;
}
GI::Sys::Systime::~Systime()
{
RTC.CTRL = RTC_PRESCALER_OFF_gc;
FPGA_RTC.RTC_PERIOD_BYTE3 = 0;
FPGA_RTC.RTC_PERIOD_BYTE2 = 0;
FPGA_RTC.RTC_PERIOD_BYTE1 = 0;
FPGA_RTC.RTC_PERIOD_BYTE0 = 0;
}
//#####################################################
void GI::Sys::Systime::sysDelay(unsigned long long milliSec)
......@@ -46,9 +46,10 @@ void GI::Sys::Systime::sysDelay(unsigned long long milliSec)
#ifdef __cplusplus
extern "C" {
#endif
ISR(RTC_OVF_vect)
ISR(RTC_vect)
{
STimerCnt += 10;
STimerCnt ++;
asm("wdr");
}
#ifdef __cplusplus
}
......
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